Design of 3.1–10.6 GHz ultra-wideband CMOS low noise amplifier with current reuse technique

A new low complexity ultra-wideband 3.1–10.6 GHz low noise amplifier (LNA), designed in a chartered 0.18 μm RFCMOS technology, is presented in this paper. The ultra-wideband LNA only consists of two simple amplifiers with an inter-stage inductor connected. The first stage utilizing a resistive current reuse and dual inductive degeneration techniques is used to attain a wideband input matching and low noise figure. A common source amplifier with inductive peaking technique as the second stage achieves high flat gain and wide the −3 dB bandwidth of the overall amplifier simultaneously. The implemented ultra-wideband LNA presents a maximum power gain of 15.6 dB, a high reverse isolation of −45 dB and a good input/output return losses are better than −10 dB in the frequency range of 3.1–10.6 GHz. An excellent noise figure (NF) of 2.8–4.7 dB was obtained in the required band with a power dissipation of 14.1 mW under a supply voltage of 1.5 V. An input-referred third-order intercept point (IIP3) is −7.1 dBm at 6 GHz. The chip area including testing pads is only 0.8 mm × 0.9 mm.     

Modern development methods and tools for embedded reconfigurable systems: A survey

Heterogeneous reconfigurable systems provide drastically higher performance and lower power consumption than traditional CPU-centric systems. Moreover, they do it at much lower costs and shorter times to market than non-reconfigurable hardware solutions. They also provide the flexibility that is often required for the engineering of modern robust and adaptive systems. Due to their heterogeneity, flexibility and potential for highly optimized application-specific instantiation, reconfigurable systems are adequate for a very broad class of applications across different industry sectors. What prevents the reconfigurable system paradigm from a broad proliferation is the lack of adequate development methodologies and electronics design tools for this kind of systems. The ideal would be a seamless compilation of a high-level computation process specification into an optimized mixture of machine code executed on traditional CPU-centric processors and on the application-specific decentralized parallel data-flow-dominated reconfigurable processors and hardware accelerators. Although much research and development in this direction was recently performed, the adequate methodologies and tools necessary to implement this compilation process as an effective and efficient hardware/software co-synthesis flow are unfortunately not yet in place. This paper focuses on the recent developments and development trends in the design methods and synthesis tools for reconfigurable systems. Reconfigurable system synthesis performs two basic tasks: system structure construction and application process mapping on the structure. It is thus more complex than standard (multi-)processor-based system synthesis for software-programmable systems that only involves application mapping. The system structure construction may involve the macro-architecture synthesis, the micro-architecture synthesis, and the actual hardware synthesis. Also, the application process mapping can be more complicated and dynamic in reconfigurable systems. This paper reviews the recent methods and tools for the macro- and micro-architecture synthesis, and for the application mapping of reconfigurable systems. It puts much attention to the relevant and currently hot topic of (re-)configurable application-specific instruction set processors (ASIP) synthesis, and specifically, ASIP instruction set extension. It also discusses the methods and tools for reconfigurable systems involving CPU-centric processors collaborating with reconfigurable hardware sub-systems, for which the main problem is to decide which computation processes should be implemented in software and which in hardware, but the hardware/software partitioning has to account for the hardware sharing by different computation processes and for the reconfiguration processes. The reconfigurable system area is a very promising, but quite a new field, with many open research and development topics. The paper reviews some of the future trends in the reconfigurable system development methods and tools. Finally, the discussion of the paper is summarized and concluded.     

Statistical analysis of large on-chip power grid networks by variational reduction scheme

One of the most critical challenges in today's CMOS VLSI design is the lack of predictability in chip performance at design stage. One of the process variabilities comes from the voltage drop variations in on-chip power distribution networks. In this paper, we present a novel analysis approach for computing voltage drops of large power grid networks under process variations. The new algorithm is very efficient and scalable for huge networks with a large number of variational variables. This approach, called variational extended truncated balanced realization (varETBR), is based on model order reduction techniques to reduce the circuit matrices before the variational simulation. It performs the parameterized reduction on the original system using variation-bearing subspaces. After the reduction, Monte Carlo based statistical simulation is performed on the reduced system and the statistical responses of the original system are obtained thereafter. varETBR calculates variational response Grammians by Monte Carlo based numerical integration considering both system and input source variations in generating the projection subspace. varETBR is very scalable for the number of variables and flexible for different variational distributions and ranges as demonstrated in experimental results. Experimental results, on a number of IBM benchmark circuits up to 1.6 million nodes, show that the varETBR can be 1900X faster than the Monte Carlo method and is much more scalable than one of the recently proposed approaches.     

What do we want specifically from the cell phone? An age related study

This study investigated the evolution of specific cell phone feature preferences among high school, undergraduate and graduate college students in Finland. Following the relevant literature review, the paper analyzed the responses of 118 high school, 268 undergraduate and 84 graduate students from educational institutions located in the metropolitan area of Tampere, Finland. The results indicate that the students in Finland appreciate the specific feature “clock”, “phone”, “high battery life”, “alarm”, and “calendar” as very important, and the specific features “TV connectivity”, “joystick”, “live TV”, “Twitter”, and “small screen size” as unimportant features. There were also significant differences in the specific feature preferences between the students between high school, undergraduate and graduate students. In addition there were differences in the way the respondents conceptualize the specific feature preferences of the cell phone. The paper concludes with a discussion regarding the academic and managerial implications.     

QoS for wireless sensor networks: Enabling service differentiation at the MAC sub-layer using CoSenS

Providing service differentiation in wireless sensor networks while proposing simple and highly scalable solution is a challenging problem. We retain the use of CSMA/CA as access protocol because of its simplicity, versatility and good scalability properties. We developed CoSenS, a Collect then Send burst Scheme, on top of it to address its weaknesses while facilitating the implementation of scheduling policies. In this article, we propose a simple and scalable service differentiation solution; we implement fixed priority and earliest deadline first on top of CoSenS. The simulation analysis shows that our solution self-adapts to the traffic variation and greatly enhances end-to-end delay, reliability and deadline meet ratio for urgent traffic while not degrading best effort traffic compared to IEEE 802.15.4 original protocol and IEEE 802.15.4 implementing these scheduling policies. Additionally, CoSenS is implemented and tested on motes. The real experimentation results validated our simulation analysis.     

A low-overhead and reliable switch architecture for Network-on-Chips

This paper proposes and evaluates Low-overhead, Reliable Switch (LRS) architecture to enhance the reliability of Network-on-Chips (NoCs). The proposed switch architecture exploits information and hardware redundancies to eliminate retransmission of faulty flits. The LRS architecture creates a redundant copy of each newly received flit and stores the redundant flit in a duplicated flit buffer that is associated with the incoming channel of the flit. Flit buffers in the LRS are equipped with information redundancy to detect probable bit flip errors. When an error is detected in a flit buffer, its duplicated buffer is used to recover the correct value of the flit. In this way, the propagation of the erroneous flits in NoC is prevented without any need to credit signals and, retransmission buffers. Using an HDL-based NoC simulator, the LRS is compared to two other widely used reliability enhancement methods: the Switch-to-Switch (S2S) and the End-to-End (E2E) methods. The simulation results show that the LRS consumes less power and provides higher performance compared to those of the E2E and S2S methods. More importantly, unlike the E2E and the S2S methods, the LRS has constant overheads, which makes it applicable in all working conditions. To validate the comparison, an analytical performance and reliability model is developed for the LRS, S2S and E2E methods. The results of the model match those obtained from the simulations while the proposed model is significantly faster.     

Characterization of natriuretic activity from posterior pituitary lobes

Previous studies have indicated the existence of natriuretic factors of hormonal nature with the posterior pituitary gland as a possible site of origin. It was in this light that a series of experiments was designed to examine the posterior pituitary for such factors. Acetic acid extracts of porcine and bovine posterior pituitary lobe tissue were subjected to gel filtration on Sephadex G-25. Several fractions in the molecular size range of 1000 were obtained which possessed potent natriuretic activity as assayed in rats. The activity of these fractions maximally increased sodium excretion to 6-8 muequiv./min, a 10- to 40-fold increase above control, when administered intraperitoneally to hydropenic, conscious rats. However, oxytocin and vasopressin, present in the posterior pituitary are natriuretic. These hormones were measured by radioimmunoassay, and invariably only those fractions which contained vasopressin and (or) oxytocin possessed natriuretic activity. Moreover, the extent of the natriuresis could be accounted for by the vasopressin and (or) oxytocin content of the test fractions. The natriuretic property of this material was abolished by treatment with thioglycollate. Further purification of natriuretic fractions by ion exchange resins, thin-layer chromatography and isoelectric focusing failed to resolve natriuretic activity from vasopressin and oxytocin. Similar results were observed following analysis of fractions isolated by gel filtration of acetic acid extracts of ventral hypothalamus tissue. The natriuretic fractions isolated from hypothalamic tissue were indistinguishable from oxytocin and vasopressin. These experiments suggest that the natriuretic activity in neurohypophyseal extracts can be attributed to oxytocin and vasopressin.     

Associations between polymorphic variety and anthropometric and biochemical variation in two New Guinea populations

During International Biological Programme studies in Papua New Guinea, on Karkar Island and at Lufa in the Eastern Highlands, information on anthropometric, biochemical and genetic characteristics was collected from the same individuals. Use has been made of this special situation to investigate whether any associations exist between genetic markers and anthropometric and biochemical variation. Those found, and which satisfy criteria established to help in distinguishing real from chance associations, include: P with haemoglobin concentration and serum albumin and cholesterol levels; acid phosphatase with serum albumin level and haemoglobin concentration; anhaptoglobinaemia and serum globulin level; haemoglobin J-Tongariki with serum phosphorus level. The associations are discussed in terms of their arising from the direct result of environmental factors modifying gene expression, chance concordance of environmental and genetic variation, or pleiotropy.