Upper bounds for blocking probabilities in large multi‐rate loss networks

In this paper, we consider large loss networks with fixed routing and multirate traffic. We use singlelink formulae and standard results on multidimensional Gaussian distributions to obtain upper bounds for blocking probabilities of new calls under light up to critical loading conditions. This is the loading regime of interest for many practical applications such as admission control in ATM networks. The main advantage of our approach is that the complexity does not scale with the size of the system, making it numerically attractive. Comparison with simulation results show that we get good upper bounds. We conclude by discussing the correlation between links in a network.     

Paraxial approximation effect on a dielectric interface analysis

We are presenting a fast new method of analysing a dielectric interface which is assumed to be cylindrically symmetrical. It is based on a multimode Gaussian beam development. Then two different cases are considered and we show the kind of results we can expect from this process. Finally, we explain in detail the relationships between the paraxial approximation and further justified simplifications which lead to an important calculation time decrease.     

Ordonnancement de paquets équitable par les disciplinesgps etdgps

Providing efficient and flexible quality of service guarantees within interogated services packet networks requires the deployment of advanced scheduling disciplines. This paper concentrates on the class of so-called fair queuing algorithms, firstly reviewing the general principle and its known approximations, then focusing on the service of adaptive applications, shedding light on the need to introduce a new scheduling paradigm, named dgps for decoupled generalized processor sharing; for the latter scheme an approximation technique is introduced and evaluated.     

COD: alternative architectures for high speed packet switching

Architectures for packet switches are approaching the limit of electronic switching speed. This raises the question of how best to utilize advances in photonic technology to enable higher speeds. The authors introduce cascaded optical delay line (COD) architectures. The COD architectures utilize an extremely simple distributed electronic control algorithm to configure the states of 2×2 photonic switches and use optical fiber delay lines to temporarily buffer packets if necessary. The simplicity of the architectures may also make them suitable for “lightweight” all-electronic implementations. For optical implementations, the number of 2×2 photonic switches used is a significant factor determining cost. The authors present a “baseline” architecture for a 2×2 buffered packet switch that is work conserving and has the first-in, first-out (FIFO) property. If the arrival processes are independent and without memory, the maximum utilization factor is ρ, and the maximum acceptable packet loss probability is ϵ, then the required number of 2×2 photonic switches is O(log(ϵ)/log(γ)), where γ=ρ²/(ρ²+4-4ρ). If one modifies the baseline architecture by changing the delay line lengths then the system is no longer work conserving and loses the FIFO property, but the required number of 2×2 photonic switches is reduced to O(log[log(ϵ)/log(γ)]). The required number of 2×2 photonic switches is essentially insensitive to the distribution of packet arrivals, but long delay lines are required for bursty traffic     

Boundary scan test,test methodology,and fault modeling

The test technique called boundary scan test (BST) offers new opportunities in testing but confronts users with new problems too. The implementation of BST in a chip has become an IEEE standard and users on board level are the next group to begin thinking about using the new possibilities. This article addresses some of the questions about changes in board-level testing and fault diagnosis. The fault model itself is also affected by using BST. Trivial items are extended with more sophisticated details in order to complete the fault model. Finally, BST appears to be a test technique that offers a high degree of detectability on board level, but for diagnosis, some additional effort has to be made.     

Experimental analysis of corner-fed printed square patch antennas

An experimental analysis is developed for the corner-fed printed square patch antenna, taking into account the width of the feeding junction and the proximity of the microstrip feedline. New accurate design relations for resonance frequency and input impedance are deduced, directly usable for the computer aided design of printed antenna arrays.<>     

Incidence of different pork quality categories in a Portuguese slaughterhouse: A survey

This study was designed to evaluate the incidence of the PSE/DFD status in a Portuguese pig slaughterhouse, covering two seasons of the year (spring and summer) in order to find out if the proportions of those poor meat quality categories were sufficient to concern the meat industry. Meat quality classification was based on the measurements of the pH(60), pH(24), drip losses and colour (L, a, b) in the longissimus dorsi muscle (between the last third and fourth ribs) of 380 pigs randomly chosen from the line. The high global incidence of PSE and likely PSE (30%) as well as DFD (10%) carcasses and the enormous variation of the meat quality between the different days of analysis proves that the pig population presents a great variation of halothane genotype and that handling procedures have to be optimized in order to decrease stress and glycogen store depletion. The percentage of PSE carcasses during the summer season was double that found in the spring, probably due to a higher environmental temperature and relative humidity.     

A 500-Mb/s quadruple data rate SDRAM interface using a skewcancellation technique

A quadruple data rate (QDR) synchronous DRAM (SDRAM) interface processing data at 500 Mb/s/pin with a 125-MHz external clock signal is presented. Since the QDR interface has a narrower data timing window, a precise skew control on data signals is required. A salient skew cancellation technique with a shared skew estimator is proposed. The skew cancellation circuit not only reduces the data signal skews on a printed circuit board down to 250 ps, but also aligns the data signals with an external clock signal. The entire interface, fabricated in a 0.35-μm CMOS technology, includes a high-speed data pattern generator and consumes 570 mW of power at 3.0-V supply. The active die area of the chip with the on-chip data pattern generator is 2.4 mm²     

Investigation of Enhancement Band Using Double Screen Frequency Selective Surfaces with Koch Fractal Geometry at Millimeter Wave Range

Numerical and theoretical investigations are presented for a double screen frequency selective surface (DSFSS) with perfectly conducting Koch fractal patch elements. The work was developed in two steps, in the first step two Koch fractal FSS screens were designed using the commercial software Ansoft Designer^TM. In the second these FSS were cascaded and separated by an air gap layer, forming the so-called DSFSS, to improve the bandwidth behavior. Thereafter, a numerical cascading technique is used to analyze the effect of the air gap on the DSFSS. The results were compared and a good agreement was observed.