A novel robust and low cost chips package and its thermalperformance

In an attempt to provide a high density memory solution, especially for workstation and PC servers, a stack chips package (SCP) has been developed. The major characteristics of SCP are as follows: (1) SCP contains a plurality of both memory chips and lead frames within a molded plastic package; (2) chip selection is made through the wire bonding option, resulting in the package with a memory capacity twice or four times that of monolithic chip; (3) plural lead frames are electrically interconnected all at once, using metal solders electroplated on the lead frame surface; and (4) SCP is found reliable and cost competitive when compared to other stack packages because it basically adopts the molded plastic packaging technology as well as the metal solder interconnection method. As electrical interconnection methods, both a fluxless soldering joint of Ag/Sn and a high-pressure mechanical joint of Ag were evaluated extensively and they successfully provided a reliable electrical conduction path without any signal degradation. Temperature cycle test and pressure cooker test were proved not to produce any micro cracks across the joint. The thermal performance of SCP was simulated by a thermal model based on finite element method (FEM) and also experimentally verified, showing good agreement within 10% deviation from simulated value. 128M SCP showed better thermal performance than stacked two TSOP's because one chip could serve as a heat sink while the other chip is activated and thermal conduction path through the lead frame is short     

Interfacial reaction between 42Sn-58Bi solder and electroless Ni-P/immersion Au under bump metallurgy during aging

The interfacial reaction between 42Sn-58Bi solder (in wt.% unless specified otherwise) and electroless Ni-P/immersion Au was investigated before and after thermal aging, with a focus on the formation and growth of an intermetallic compound layer, consumption of under bump metallurgy (UBM), and bump shear strength. The immersion Au layer with thicknesses of 0 μm (bare Ni), 0.1 μm, and 1 μm was plated on a 5-μm-thick layer of electroless Ni-P (with 14–15 at.% P). The 42Sn-58Bi solder balls were then fabricated on three different UBM structures by using screen printing and pre-reflow. A Ni₃Sn₄ layer formed at the joint interface after the pre-reflow for all three UBM structures. On aging at 125°C, a quaternary phase, identified as Sn₇₇Ni₁₅Bi₆Au₂, was observed above the Ni₃Sn₄ layer in the UBM structures that contain Au. The thick Sn₇₇Ni₁₅Bi₆Au₂ layer degraded the integrity of the solder joint, and the shear strength of the solder bump was about 40% less than the nonaged joints.     

High-speed driving method using bipolar scan waveform in AC plasma display panel

This paper proposes a new high-speed driving method using the bipolar scan waveform with a scan width of 1 /spl mu/s in an ac-plasma display panel. The bipolar scan waveform in an address period consists of a two-step pulse with two different polarities, i.e., a forward scan pulse with a negative polarity and reverse scan pulse with a positive polarity, which can produce two address discharges, including a primary address discharge for generating wall charges and secondary address discharge for accumulating wall charges. To produce the fast address discharge stably using the bipolar scan pulse during an address period, a new reset waveform is designed based on a V/sub t/ close curve analysis, and the address discharge characteristics examined under various reset and address waveforms. As a result of adopting the proposed driving method, a high-speed address with a scan width of 1 /spl mu/s is successfully obtained when using a checkered pattern on a 4-in test panel.     

Facile Fabrication and Superparamagnetism of Silica‐Shielded Magnetite Nanoparticles on Carbon Nitride Nanotubes

Using conventional methods to synthesize magnetic nanoparticles (NPs) with uniform size is a challenging task. Moreover, the degradation of magnetic NPs is an obstacle to practical applications. The fabrication of silica‐shielded magnetite NPs on carbon nitride nanotubes (CNNTs) provides a possible route to overcome these problems. While the nitrogen atoms of CNNTs provide selective nucleation sites for NPs of a particular size, the silica layer protects the NPs from oxidation. The morphology and crystal structure of NP–CNNT hybrid material is investigated by transmission electron microscopy (TEM) and X‐ray diffraction. In addition, the atomic nature of the N atoms in the NP–CNNT system is studied by near‐edge X‐ray absorption fine structure spectroscopy (nitrogen K‐edge) and calculations of the partial density of states based on first principles. The structure of the silica‐shielded NP–CNNT system is analyzed by TEM and energy dispersive X‐ray spectroscopy mapping, and their magnetism is measured by vibrating sample and superconducting quantum interference device magnetometers. The silica shielding helps maintain the superparamagnetism of the NPs; without the silica layer, the magnetic properties of NP–CNNT materials significantly degrade over time.     

Effects of channel thickness variation on bias stress instability of InGaZnO thin-film transistors

Here, we report on the effects of channel (or active) layer thickness on the bias stress instability of InGaZnO (IGZO) thin-film transistors (TFTs). The investigation on variations of TFT characteristics under the electrical bias stress is very crucial for commercial applications. In this work, the initial electrical characteristics of the tested TFTs with different channel layer thicknesses (40, 50, and 60 nm) are performed. Various gate bias (V_GS) stresses (10, 20, and 30 V) are then applied to the tested TFTs. For all V_GS stresses with different channel layer thickness, the experimentally measured threshold voltage shift (ΔV_th) as a function of stress time is precisely modeled with stretched-exponential function. It is indicated that the ΔV_th is generated by carrier trapping but not defect creation. It is also observed that the ΔV_th shows incremental behavior as the channel layer thickness increases. Thus, it is verified that the increase of total trap states (N_T) and free carriers resulted in the increase of ΔV_th as the channel layer thickness increases.     

Novel zero-voltage and zero-current-switching (ZVZCS) full-bridge PWM converter using coupled output inductor

A novel zero-voltage and zero-current-switching (ZVZCS) full-bridge pulse-width-modulated (PWM) converter is proposed to improve the previously proposed ZVZCS full-bridge PWM converters. By employing a simple auxiliary circuit with neither lossy components nor active switches, soft-switching of the primary switches is achieved. The proposed converter has many advantages such as simple auxiliary circuit, high efficiency, low voltage stress of the rectifier diode and self-adjustment of the circulating current, which make the proposed converter attractive for the high voltage and high power applications. The principles of operation and design considerations are presented and verified on the 4 kW experimental converter operating at 80 kHz.     

Parallel feed travelling wave distributed pin photodetectors withintegrated MMI couplers

The fabrication and performance of a parallel feed travelling wave photodetector with pin diodes operating at 1550 nm is presented. A parallel optical feed using an integrated multimode interference (MMI) power splitter helps increase the maximum linear photocurrent through a more uniform distribution of photocurrent. The maximum DC linear current measured is 52.2 mA. Maximum linear RF power at 10 GHz was 9 dBm     

A novel droop method for converter parallel operation

For the converter parallel operation, the current sharing between modules is important for the reliability of the system. Among several current sharing schemes, the droop method needs no interconnection between modules, which implies true redundancy. But the droop method has poor voltage regulation and poor current sharing characteristics. In this paper, a novel droop method is proposed for the converter parallel operation, which adaptively controls the reference voltage of each module. This greatly improves the output voltage regulation and the current sharing of the conventional droop method. The analysis of the proposed method and design procedure are provided and experimental results verify the excellent performance of the proposed method     

A novel spectrum sensing scheme with sensing time optimization for energy-efficient CRSNs

Wireless Networks - The cognitive radio technology enables secondary users (SUs) to occupy licensed bands when primary users (PUs) are not occupy them. Spectrum sensing is a key technology for SUs...     

Estimation of anomaly location and size using electrical impedance tomography

We developed a new algorithm that estimates locations and sizes of anomalies in electrically conducting medium based on electrical impedance tomography (EIT) technique. When only the boundary current and voltage measurements are available, it is not practically feasible to reconstruct accurate high-resolution cross-sectional conductivity or resistivity images of a subject. In this paper, we focus our attention on the estimation of locations and sizes of anomalies with different conductivity values compared with the background tissues. We showed the performance of the algorithm from experimental results using a 32-channel EIT system and saline phantom. With about 1.73% measurement error in boundary current-voltage data, we found that the minimal size (area) of the detectable anomaly is about 0.72% of the size (area) of the phantom. Potential applications include the monitoring of impedance related physiological events and bubble detection in two-phase flow. Since this new algorithm requires neither any forward solver nor time-consuming minimization process, it is fast enough for various real-time applications in medicine and nondestructive testing.