Comparison of hole mobility in LOCOS-isolated thin-film SOIp-channel MOSFET's fabricated on various SOI substrates

The hole mobility of LOCOS-isolated thin-film silicon-on-insulator (SOI) p-channel MOSFET's fabricated on SOI substrates with different buried oxide thickness has been investigated. Two types of SOI wafers are used as a substrate: (1) SIMOX wafer with 100-nm buried oxide and (2) bonded SOI wafer with 100-nm buried oxide. Thin-film SOI p-MOSFET's fabricated on SIMOX wafer have hole mobility that is about 10% higher than that on bonded SOI wafer. This is caused by the difference in the stress under which the silicon film is after gate oxidation process. This increased hole mobility leads to the improved propagation delay time by about 10%     

Lower bound on BER of finite-length turbo codes based on EXIT characteristics

We present a generalized extrinsic information transfer characteristics of the iterative turbo decoding algorithm. By using this tool, we obtain a lower bound on the bit error rate performance of the finite-length turbo codes showing a gentle waterfall over a wide waterfall region.     

A method for generating Simulated nighttime road images under automotive headlamp lights

This study proposes a new calculation method for generating real nighttime lamp-lit images. In order to improve the color appearance in the prediction of a nighttime lamp-lighted road scene, the lamp-lit image is synthesized based on spectral distribution using the estimated local spectral distribution of the headlamps and the surface reflectance of every object. The principal component analysis method is introduced to estimate the surface color of an object and the local spectral distribution of the headlamps is calculated based on the illuminance data and spectral distribution of the illuminating headlamps. High-intensity discharge and halogen lamps are utilized to create beam patterns and captured road scenes are used as background images to simulate actual headlamp-lit images on a monitor. As a result, the reproduced images presented a color appearance that was very close to a real nighttime road image illuminated by single and multiple headlamps.     

CML-type MOnostable BIstable logic element (MOBILE) using InP-based monolithic RTD/HBT technology

A new CML-type monostable/bistable logic element IC is fabricated using monolithically integrated resonant tunnelling diodes (RTDs) and InP/InGaAs heterojunction bipolar transistors (HBTs). The D-flip-flop function of the fabricated circuit is confirmed up to 20 Gbit/s at room temperature. This result indicates the potential of the RTD/HBT technology for high-speed logic applications.     

A fully differential LC-VCO using a new varactor control structure

This paper presents a fully differential inductor-capacitor voltage-controlled oscillator (LC-VCO) with a new differentially-tuned varactor structure. The proposed LC-VCO has lower phase noise and better robustness to the injected common-mode noise than the differentially-tuned LC-VCO using the previous antiparallel structure. The LC-VCO implemented using 0.5-/spl mu/m SiGe BiCMOS technology is tunable from 4.251 to 4.428 GHz and the measured phase noise is -119 dBc/Hz at 1-MHz offset over the entire tuning range. Its core current is only 1.7 mA at 2.5-V supply voltage.     

An InGaAs-InP HBT differential transimpedance amplifier with 47-GHz bandwidth

Return-to-zero differential phase-shift keying applications require a differential amplifier with high bandwidth, high gain, low noise, and good input impedance match. In this paper, we describe an InGaAs-InP heterostructure bipolar transistor differential transimpedance amplifier with high bandwidth of 47 GHz and high gain of 56 dB-/spl Omega/. The input-referred current noise is less than 35 pA//spl radic/Hz over the measurement range up to 40 GHz.     

Improved performance of Si-based spiral inductors

Conventional spiral inductors on silicon wafer have suffered low quality (Q) factor due to substrate loss. In this work, a technique that combines optimized shielding poly and proton implantation treatment is utilized to improve inductor Q-value. The optimized poly-silicon and proton-bombarded substrate have added 37% and 54% increment to the Q-value of inductors, respectively. If two techniques are combined, a phenomenal Q-value increment as high as 122% of 4-nH spiral inductors can be realized. The combination of the two means has created a multiplication of their individual contribution rather than addition. The technique used in this work shall become a critical measure to put inductors on silicon substrate with satisfactory performance for Si-based radio frequency integrated circuit applications.     

SOSP: an efficient multicast fault isolation scheme for multi-source sessions

This paper proposes a one-way source probing mechanism for fault isolation in multi-source multicast sessions. Routers involved in multicast record a routing path based on periodic probes from sources, and receivers isolate a fault region using the probes. We introduce a probe suppression mechanism to enhance the performance. The proposed scheme reduces message complexity and enhances fault isolation latency, which improves scalability. Furthermore, an analytical formula is proposed to estimate suppression time, which provides maximum performance for a given network status.     

A fully integrated 24-dBm CMOS power amplifier for 802.11a WLAN applications

A fully integrated 24-dBm complementary metal oxide semiconductor (CMOS) power amplifier (PA) for 5-GHz WLAN applications is implemented using 0.18-/spl mu/m CMOS foundry process. It consists of differential three-stage amplifiers and fully integrated input/output matching circuits. The amplifier shows a P/sub 1/ of 21.8 dBm, power added efficiency of 13%, and gain of 21 dB, respectively. The saturated output power is above 24.1 dBm. This shows the highest output power among the reported 5-GHz CMOS PAs as well as completely satisfying IEEE 802.11a transmitter back off requirement.     

A dry-patterned Cu(Mg) alloy film as a gate electrode in a thin-film transistor liquid crystal display

The annealing of a Cu(4.5at.%Mg)/SiO₂/Si structure in ambient O₂ at 10 mtorr and 300–500°C allows for the out-diffusion of the Mg to the Cu surface, forming a thin MgO (15 nm) layer on the surface. The surface MgO layer was patterned and successfully served as a hard mask for the subsequent dry etching of the underlying Mg-depleted Cu films using an O₂ plasma and hexafluoroacetylacetone (H(hfac)) chemistry. The resultant MgO/Cu structure, with a taper slope of about 30°, shows the feasibility of dry etching of Cu(Mg) alloy films using a surface MgO mask scheme. A dry-etched Cu(4.5at.%Mg) gate a-Si:H thin-film transistor (TFT) has a field-effect mobility of 0.86 cm²/Vs, a subthreshold swing of 1.08 V/dec, and a threshold voltage of 5.7 V. A novel process for the dry etching of Cu(Mg) alloy films that eliminates the use of a hard mask, such as Ti, and results in a reduction in the process steps is reported for the first time in this work.