Synthesis,Characterization, and drug release study of acrylamide‐co‐itaconic acid based smart hydrogel

A new kind of pH and temperature responsive poly(acrylamide‐co‐itaconic acid) hydrogel was prepared by free radical polymerization using ammonium persulfate as initiator and different comonomer ratios. The hydrogels were characterized in terms of chemical composition, swelling‐deswelling behavior, morphology, crystallographic behavior, and drug release properties. All the hydrogels showed high swelling ability in aqueous solutions, the maximum being at pH 7. Swelling decreased on either side of pH 7 (i.e., both in acidic and alkaline region) and increased with increase in temperature. The hydrogel with 10 mol% itaconic acid (IA) absorbed maximum water among the copolymer gels. The cellular structures of the hydrogels were clearly revealed by microscopic analysis and SEM pictures. Swelling of the gels in water followed non‐Fickian type of diffusion principle. The hydrogel was proved to be a controlled release vehicle, for example in drug delivery by using its smart properties. The hydrogel with 10 mol% IA also absorbed maximum amount of drug (ascorbic acid) under study. Incorporation of drug in hydrogel matrix was established from XRD peak analysis. POLYM. ENG. SCI., 55:113–122, 2015. © 2014 Society of Plastics Engineers     

Distributed fault-tolerant topology control in wireless multi-hop networks

In wireless multi-hop and ad-hoc networks, minimizing power consumption and at the same time maintaining desired properties of the network topology is of prime importance. In this work, we present a distributed algorithm for assigning minimum possible power to all the nodes in a static wireless network such that the resultant network topology is k-connected. In this algorithm, a node collects the location and maximum power information from all nodes in its vicinity, and then adjusts the power of these nodes in such a way that it can reach all of them through k optimal vertex-disjoint paths. The algorithm ensures k-connectivity in the final topology provided the topology induced when all nodes transmit with their maximum power is k-connected. We extend our topology control algorithm from static networks to networks having mobile nodes. We present proof of correctness for our algorithm for both static and mobile scenarios, and through extensive simulation we present its behavior.     

Traffic grooming,routing, and wavelength assignment in an optical WDM mesh networks based on clique partitioning

In wavelength routed optical networks, the number of wavelength channels is limited due to several constraints and each wavelength as well as each lightpath support traffic in the Gbps range. On the other hand, the traffic requested by an individual connection is still in the Mbps range. Therefore, to utilize the network resources (such as bandwidth and transceivers) effectively, several low-speed traffic streams have to be efficiently groomed or multiplexed into one or more high-speed lightpaths. The grooming problem of a static demand is considered as an optimization problem. In this work, we have investigated the traffic grooming problem with the objective of maximizing the network throughput for wavelength-routed mesh networks and map this problem to the clique partitioning problem. We have proposed an algorithm to handle general multi-hop static traffic grooming based on the clique partitioning concept. The efficiency of our approach has been established through extensive simulation on different sets of traffic demands with different bandwidth granularities for different network topologies and compared the approach with existing algorithms.     

My words for your pizza: An analysis of persuasive narratives in online crowdfunding

We analyze charity requests registered on the Random Acts of Pizza online community and examine the content of postings and non-content characteristics to identify features that are associated with the success of donation. We find that the presence of rational and credible appeals in a message increases the likelihood of receiving a donation, whereas the mere presence of negative emotional appeal does not do so. Our research is useful for those who like to make persuasive charity requests on online platforms.     

Balance testing and balance-testable design of logic circuits

We propose a low-cost method for testing logic circuits, termed balance testing, which is particularly suited to built-in self testing. Conceptually related to ones counting and syndrome testing, it detects faults by checking the difference between the number of ones and the number of zeros in the test response sequence. A key advantage of balance testing is that the testability of various fault types can be easily analyzed. We present a novel analysis technique which leads to necessary and sufficient conditions for the balance testability of the standard single stuck-line (SSL) faults. This analysis can be easily extended to multiple stuck-line and bridging faults. Balance testing also forms the basis for design for balance testability (DFBT), a systematic DFT technique that achieves full coverage of SSL faults. It places the unit under test in a low-cost framework circuit that guarantees complete balance testability. Unlike most existing DFT techniques, DFBT requires only one additional control input and no redesign of the underlying circuit is necessary. We present experimental results on applying balance testing to the ISCAS 85 benchmark circuits, which show that very high fault coverage is obtained for large circuits even with reduced deterministic test sets. This coverage can always be made 100% either by adding tests or applying DFBT.This research was supported by the National Science Foundation under Grant No. MIP-9200526. Parts of this paper were published in preliminary form in Proc. 23rd Symp. Fault-Tolerant Computing, Toulouse, June 1993, and in Proc. 31st Design Automation Conf, San Diego, June 1994.     

Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with nonexhaustive test sets

The design of efficient time compression support hardware for built-in self-testing (BIST) is of great importance in the design and manufacture of VLSI circuits. The test data outputs in BIST are ultimately compressed by time compaction hardware, commonly called a response analyzer, into signatures. Several output response compaction techniques to aid in the synthesis of such support circuits already exist in literature, and parity bit signature coupled with exhaustive testing is already well known to have certain very desirable properties in this context. This paper reports new time compaction techniques utilizing the concept of parity bit signature that facilitates implementing such support circuits using nonexhaustive or compact test sets, with the primary objective of minimizing the storage requirements for the circuit under test (CUT) while maintaining the fault coverage information as best as possible.     

Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes

We present an analysis of test application time for test data compression techniques that are used for reducing test data volume and testing time in system-on-a-chip (SOC) designs. These techniques are based on data compression codes and on-chip decompression. The compression/decompression scheme decreases test data volume and the amount of data that has to be transported from the tester to the SOC. We show via analysis as well as through experiments that the proposed scheme reduces testing time and allows the use of a slower tester. Results on test application time for the ISCAS'89 circuits are obtained using an ATE testbench developed in VHDL to emulate ATE functionality.     

Cumulative balance testing of logic circuits

We present a new test response compression method called cumulative balance testing (CBT) that extends both balance testing and accumulator compression testing. CBT uses an accumulated balance signature, and it guarantees very high error coverage (over 99%) for various error models. We demonstrate that the single stuck-line (SSL) fault coverage of CBT for many of the ISCAS 85 combinational benchmark circuits is 100%, and for all but one circuit, the fault coverage is over 99.5%. To make processor circuits self-testing, any existing accumulators and counters can be exploited to implement CBT. Its ease of implementation, provably high error coverage, and exceptionally high SSL fault coverage, even with reduced (nonexhaustive) test sets, make CBT suitable for the built-in self testing of processor circuits that require a guaranteed level of test confidence     

Capacitance of dielectric coated cylinder of finite axial lengthand truncated cone isolated in free space

The capacitance of dielectric coated metallic cylinder and truncated cone are evaluated using the method of moments based on the pulse function and point matching. The analysis is based on the boundary condition for the potential on the conductor surface and the normal component of the displacement density at the dielectric-free space interface. The total free charge on the conductor surface is found from the inversion of a matrix partitioned into submatrices. Numerical data on the capacitance and charge distribution are presented