Design procedure of class-E amplifier for off-nominal operation at 50% duty ratio

Design equations for satisfying the off-nominal operating condition [i.e., only the zero-voltage switching (ZVS) condition] of the Class-E amplifier with a linear shunt capacitance at a duty ratio D=0.5 are derived. A new parameter s (V/s), called the slope of switch voltage when the switch turns on is introduced to obtain an image of the distance from the nominal conditions. By examining off-nominal Class-E operation degree of the design freedom of the Class-E amplifier increases by one. In addition various amplifier parameters such as operating frequency, output power, and load resistance range can be set as design specifications. For example, the peak switch voltage and switch current can be taken into account in the design procedure. Examples of a design procedure of the Class-E amplifier for off-nominal operation are given. The theoretical results were verified with PSpice simulation and experiments.     

Mobile Device Security Using Transient Authentication

Mobile devices are vulnerable to theft and loss due to their small size and the characteristics of their common usage environment. Since they allow users to work while away from their desk, they are most useful in public locations and while traveling. Unfortunately, this is also where they are most at risk. Existing schemes for securing data either do not protect the device after it is stolen or require bothersome reauthentication. Transient Authentication lifts the burden of authentication from the user by use of a wearable token that constantly attests to the user's presence. When the user departs, the token and device lose contact and the device secures itself. We show how to leverage this authentication framework to secure all the memory and storage locations on a device into which secrets may creep. Our evaluation shows this is done without inconveniencing the user, while imposing a minimal performance overhead     

Optimised anaerobic treatment of house-sorted biodegradable waste and slaughterhouse waste in a high loaded half technical scale digester.

Anaerobic co-digestion of organic wastes from households, slaughterhouses and meat processing industries was optimised in a half technical scale plant. The plant was operated for 130 days using two different substrates under organic loading rates of 10 and 12 kgCOD.m(-3).d(-1). Since the substrates were rich in fat and protein components (TKN: 12 g.kg(-1) the treatment was challenging. The process was monitored on-line and in the laboratory. It was demonstrated that an intensive and stable co-digestion of partly hydrolysed organic waste and protein rich slaughterhouse waste can be achieved in the balance of inconsistent pH and buffering NH4-N. In the first experimental period the reduction of the substrate COD was almost complete in an overall stable process (COD reduction >82%). In the second period methane productivity increased, but certain intermediate products accumulated constantly. Process design options for a second digestion phase for advanced degradation were investigated. Potential causes for slow and reduced propionic and valeric acid degradation were assessed. Recommendations for full-scale process implementation can be made from the experimental results reported. The highly loaded and stable codigestion of these substrates may be a good technical and economic treatment alternative.     

The Influence and Interpretation of Surface Parameters for Wetting Transitions in Ternary Mixtures

Starting from a microscopic Hamiltonian defined on a semi-infinite cubic lattice, and employing a mean-field approximation, the surface parameters relevant for wetting in confined ternary mixtures are derived. These are found in terms of the microscopic coupling constants, and yield a physical interpretation of their origins. In comparison with the standard expression for the surface free-energy density, several new terms arising from the derivation are identified. The influence of the surface parameters on a predicted unbinding transition in a mixture of oil, water, and amphiphile demonstrate that existing results are robust to the addition of the extra surface terms.     

A CMOS multichannel 10-Gb/s transceiver

We describe a CMOS multichannel transceiver that transmits and receives 10 Gb/s per channel over balanced copper media. The transceiver consists of two identical 10-Gb/s modules. Each module operates off a single 1.2-V supply and has a single 5-GHz phase-locked loop to supply a reference clock to two transmitter (Tx) channels and two receiver (Rx) channels. To track the input-signal phase, the Rx channel has a clock recovery unit (CRU), which uses a phase-interpolator-based timing generator and digital loop filter. The CRU can adjust the recovered clock phase with a resolution of 1.56 ps. Two sets of two-channel transceiver units were fabricated in 0.11-/spl mu/m CMOS on a single test chip. The transceiver unit size was 1.6 mm /spl times/ 2.6 mm. The Rx sensitivity was 120-mVp-p differential with a 70-ps phase margin for a common-mode voltage ranging from 0.6 to 1.0 V. The evaluated jitter tolerance curve met the OC-192 specification.     

Information outage probability of distributed STBCs over Nakagami fading channels

Space-time block codes (STBCs) allow utilising the diversity provided by multiple-input-multiple-output (MIMO) communication channels, thereby decreasing the outage probability for a given communication rate. The contribution of this letter is the derivation of a closed-form expression of the outage probability of distributed STBCs deployed over Nakagami flat fading channels with different channel gains and fading parameters.     

Analysis of feedback for higher order polarization-mode dispersion mitigation of NRZ 40-Gb/s optical transmission

First-order polarization-mode dispersion (PMD) compensation by means of a polarization controller and a differential delay line is not sufficient to guarantee error-free transmission for 40-Gb/s channels when higher order effects severely increase signal distortion. Higher order mitigation is possible by cascading more than one first-order block. However, only two-stage or three-stage devices remain simple enough to be actually controlled. The performance of such higher order PMD compensators is evaluated by means of numerical simulations. Two different feedback signals have been used, demonstrating that first-order and higher order PMD distortion of nonreturn-to-zero (NRZ) pulses at 40 Gb/s can be strongly mitigated for instantaneous values of the differential group delay (DGD) up to the bit slot, when the compensator is properly controlled.