A grey approach for forecasting in a supply chain during intermittentdisruptions

The supply chains today have become vulnerable to frequent disruptions, and with continuing emphasis on efficiency, lacks robustness to deal with them. A part of the solution lies in forecasting the disruption beforehand and the other part in knowing which policies will suit such disrupted conditions best. Accurate and immediate forecasts are a must in a supply chain and hence play a huge role in stabilizing. This study compares the performance of three established forecasting methods (moving average, weighted moving average and exponential smoothing) as well as grey prediction method, during disruptions and stable situations. The experiments are performed in the form of discrete event simulation, on a four stage beer game settings. The results show that moving average and weighted moving average methods become incompetent during disruptions, and are useful only during stable times, when the demand hovers around a predefined mean value. Exponential smoothing and grey method seems to give better results during disruptions and also during stable times in upstream tiers. Grey prediction method in particular is the best method when the disruption frequency is high and also when the disruption impact is gradual rather than sudden.     

Spatial Wavefunction-Switched (SWS) InGaAs FETs with II–VI Gate Insulators

This paper presents the implementation of a novel InGaAs field-effect transistor (FET), using a ZnSe-ZnS-ZnMgS-ZnS stacked gate insulator, in a spatial wavefunction-switched (SWS) structural configuration. Unlike conventional FETs, SWS devices comprise two or more asymmetric coupled quantum wells (QWs). This feature enables carrier transfer vertically from one quantum well to another or laterally to the wells of adjacent SWS-FET devices by manipulation of the gate voltages (V _g). Observation of an extra peak (near both accumulation and inversion regions) in the capacitance–voltage data in an InGaAs-AlInAs two-quantum-well SWS structure is presented as evidence of spatial switching. The peaks are attributed to the appearance of carriers first in the lower well and subsequently their transfer to the upper well as the gate voltage is increased. The electrical characteristics of a fabricated SWS InGaAs FET are also presented along with simulations of capacitance–voltage (C–V) behavior, showing the effect of wavefunction switching between wells. Finally, logic operations involving simultaneous processing of multiple bits in a device, using coded spatial location of carriers in quantum well channels, are also described.     

Biometric cryptosystems: issues and challenges

In traditional cryptosystems, user authentication is based on possession of secret keys; the method falls apart if the keys are not kept secret (i.e., shared with non-legitimate users). Further, keys can be forgotten, lost, or stolen and, thus, cannot provide non-repudiation. Current authentication systems based on physiological and behavioral characteristics of persons (known as biometrics), such as fingerprints, inherently provide solutions to many of these problems and may replace the authentication component of traditional cryptosystems. We present various methods that monolithically bind a cryptographic key with the biometric template of a user stored in the database in such a way that the key cannot be revealed without a successful biometric authentication. We assess the performance of one of these biometric key binding/generation algorithms using the fingerprint biometric. We illustrate the challenges involved in biometric key generation primarily due to drastic acquisition variations in the representation of a biometric identifier and the imperfect nature of biometric feature extraction and matching algorithms. We elaborate on the suitability of these algorithms for digital rights management systems.     

Optical backbone and control of attocell network

Photonic Network Communications - For serving futuristic applications like distributed robotic systems with robots equipped with humanoid intelligence, wireless access to high-performance computing...     

Analysis of a Disc-Loaded Circular Waveguide for Interaction Impedance of a Gyrotron Amplifier

A rigorous electromagnetic analysis of a circular waveguide loaded with axially periodic annular discs was developed in the fast-wave regime, considering finite axial disc thickness and taking into account the effect of higher order space harmonics in the disc-free region and higher order modal harmonics in the disc-occupied region of the structure. The quality of the disc-loaded circular waveguide was evaluated with respect to its azimuthal interaction impedance that has relevance to the gain of a gyrotron millimeter-wave amplifier (gyro-traveling-wave tube) in which such a loaded waveguide finds application as a wideband interaction structure. The results of electromagnetic analysis of the structure with respect to both the dispersion and azimuthal interaction impedance characteristics were validated against the commercially available code: high frequency structure simulator (HFSS). The analysis predicts that the value of the interaction impedance at a given frequency decreases with the increase of the disc hole radius and disc periodicity. The change of the axial disc thickness does not significantly change the value of the interaction impedance though it shifts the frequency range over which appreciable interaction impedance is obtained. Out of the three disc parameters, namely the disc hole radius, thickness and periodicity, the lattermost is most effective in controlling the value of the azimuthal interaction impedance. However, the passband of frequencies and the center frequency of the passband both decrease with the increase of the disc periodicity. Moreover, the disc periodicity that provides large azimuthal interaction impedance would in general be different from that giving the desired dispersion shape for wideband interaction in a gyro-TWT, suggesting a trade-off in the value of the disc periodicity to be chosen.     

Indium Gallium Arsenide Quantum Dot Gate Field-Effect Transistor Using II–VI Tunnel Insulators Showing Three-State Behavior

This paper presents an indium gallium arsenide (InGaAs) quantum dot gate field-effect transistor (QDG-FET) that exhibits an intermediate “i” state in addition to the conventional ON and OFF states. The QDG-FET utilized a II–VI gate insulator stack consisting of lattice-matched ZnSe/ZnS/ZnMgS/ZnS/ZnSe for its high-κ and wide-bandgap properties. Germanium oxide (GeO _x )-cladded germanium quantum dots were self-assembled over the gate insulator stack, and they allow for the three-state behavior of the device. Electrical characteristics of the fabricated device are also presented.     

Critical Layer Thickness in Exponentially Graded Heteroepitaxial Layers

Exponentially graded semiconductor layers are of interest for use as buffers in heteroepitaxial devices because of their tapered dislocation density and strain profiles. Here we have calculated the critical layer thickness for the onset of lattice relaxation in exponentially graded In _x Ga_1?x As/GaAs (001) heteroepitaxial layers. Upwardly convex grading with \( x = x_{\infty } \left( {1 - {\rm e}^{ - \gamma /y} } \right) \) was considered, where y is the distance from the GaAs interface, γ is a grading length constant, and x _∞ is the limiting mole fraction of In. For these structures the critical layer thickness was determined by an energy-minimization approach and also by consideration of force balance on grown-in dislocations. The force balance calculations underestimate the critical layer thickness unless one accounts for the fact that the first misfit dislocations are introduced at a finite distance above the interface. The critical layer thickness determined by energy minimization, or by a detailed force balance model, is approximately \( h_{\rm{c}} \approx <Exponentially graded semiconductor layers are of interest for use as buffers in heteroepitaxial devices because of their tapered dislocation density and strain profiles. Here we have calculated the critical layer thickness for the onset of lattice relaxation in exponentially graded In _x Ga_1−x As/GaAs (001) heteroepitaxial layers. Upwardly convex grading with x = x_￥ ( 1 - e ^{- g/y} ) x = x_{\infty } \left( {1 - {\rm e}^{ - \gamma /y} } \right) was considered, where y is the distance from the GaAs interface, γ is a grading length constant, and x _∞ is the limiting mole fraction of In. For these structures the critical layer thickness was determined by an energy-minimization approach and also by consideration of force balance on grown-in dislocations. The force balance calculations underestimate the critical layer thickness unless one accounts for the fact that the first misfit dislocations are introduced at a finite distance above the interface. The critical layer thickness determined by energy minimization, or by a detailed force balance model, is approximately h_c ? < h_{\rm{c}} \approx < Although these results were developed for exponentially graded In _x Ga_1−x As/GaAs (001), they may be generalized to other material systems for application to the design of exponentially graded buffer layers in metamorphic device structures such as modulation-doped field-effect transistors and light-emitting diodes.     

INSPAD: a system for automatic bond pad inspection

A method of detecting probe mark defects in semiconductor bond pads is presented that uses digitized images of color Polaroid photographs from an optical microscope. INSPAD inspects the bond pads in a magnified IC circuit image taken after the electrical testing stage. These are: probe marks must not extend beyond pad boundaries such that they damage glassivation; scratches on the bond pads must not exceed 50% of the bond pad width; and the probe marks must not exceed 25% of the bond pad area. Three types of commonly used bond pad geometries have been addressed. Morphological filtering is performed on the bond pad, to isolate and identify the major probe mark regions. Inspection of each pad takes approximately 2 to 3 s on an Apollo DN-4000 workstation which makes it suitable for real-time applications     

A 44 GHz monolithic semiconductor dipole antenna

Monolithic semiconductor antennas integrated with a diode detector have been fabricated using silicon-on-sapphire technology. The performance of these antennas is analyzed on the basis of earlier theoretical work on imperfectly conducting/resistive cylindrical dipoles. The measured radiation patterns of semiconductor antennas are compared with those of the corresponding printed metal dipoles.