Probing stress effects in HfO2 gate stacks with time dependent measurements

Effects of constant voltage stress (CVS) on gate stacks consisting of an ALD HfO₂ dielectric with various interfacial layers were studied with time dependent sensing measurements: DC I–V, pulse I–V, and charge pumping (CP) at different frequencies. The process of injected electron trapping/de-trapping on pre-existing defects in the bulk of the high-κ film was found to constitute the major contribution to the time dependence of the threshold voltage (V_t) shift during stress. The trap generation observed with the low frequency CP measurements is suggested to occur within the interfacial oxide layer or the interfacial layer/high-κ interface, with only a minor effect on V_t.     

Control of circulating current in two parallel three-phase boost rectifiers

One unique feature in parallel three-phase converters is a potential zero-sequence circulating current. To avoid the circulating current, most present technology uses an isolation approach, such as transformers or separate power supplies. This paper proposes a parallel system where individual converters connect both AC and DC sides directly without additional passive components to reduce size and cost of the overall parallel system. In this case, the control of the circulating current becomes an important objective in the converter design. This paper: (1) develops an averaged model of the parallel converters based on a phase-leg averaging technique; (2) a zero-sequence model is then developed to predict the dynamics of the zero-sequence current; (3) based on the zero-sequence model, this paper introduces a new control variable, which is associated with space-vector modulation; (4) a strong zero-sequence current control loop is designed to suppress the circulating current; and (5) simulation and experimental results validate the developed model and the proposed control scheme.     

A simple method for measuring the cell gap of a reflective twisted nematic LCD

A simple method is demonstrated for measuring the cell gap of reflective twisted nematic (RTN) liquid crystal (LC) cells. This method utilizes a single laser beam and crossed polarizer configuration such that Fabry-Perot effect and surface reflection are eliminated. Experimental results agree well with theory.     

New Syndrome Check Error Estimation and Its Concatenated Coding

A low-complexity and high performance SCEE (Syndrome Check Error Estimation) decoding method for convolutional codes and its concatenated SCEE/RS (Reed–Solomon) coding scheme are proposed. First, we describe the operation of the decoding steps in the proposed algorithm. Then deterministic values on the decoding operation are derived when some combination of predecoder-reencoder is used. Computer simulation results show that the computational complexity of the proposed SCEE decoder is significantly reduced compared to that of conventional Viterbi decoder without degradation of the P_e performance. Also, simulation results of BER performance of the concatenated SCEE/Hard Decision Viterbi (HD-Viterbi) and SCEE/RS (Reed–Solomon) codes are presented.     

Sub-50 nm P-channel FinFET

High-performance PMOSFETs with sub-50-nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects. This vertical double-gate SOI MOSFET features: 1) a transistor channel which is formed on the vertical surfaces of an ultrathin Si fin and controlled by gate electrodes formed on both sides of the fin; 2) two gates which are self-aligned to each other and to the source/drain (S/D) regions; 3) raised S/D regions; and 4) a short (50 nm) Si fin to maintain quasi-planar topology for ease of fabrication. The 45-nm gate-length p-channel FinFET showed an I_dsat of 820 μA/μm at V_ds=V_gs=1.2 V and T _ox=2.5 mm. Devices showed good performance down to a gate-length of 18 nm. Excellent short-channel behavior was observed. The fin thickness (corresponding to twice the body thickness) is found to be critical for suppressing the short-channel effects. Simulations indicate that the FinFET structure can work down to 10 nm gate length. Thus, the FinFET is a very promising structure for scaling CMOS beyond 50 nm     

Thermally Controlled,Patterned Graphene Transfer Printing for Transparent and Wearable Electronic/Optoelectronic System

Graphene has been highlighted as a platform material in transparent electronics and optoelectronics, including flexible and stretchable ones, due to its unique properties such as optical transparency, mechanical softness, ultrathin thickness, and high carrier mobility. Despite huge research efforts for graphene‐based electronic/optoelectronic devices, there are remaining challenges in terms of their seamless integration, such as the high‐quality contact formation, precise alignment of micrometer‐scale patterns, and control of interfacial‐adhesion/local‐resistance. Here, a thermally controlled transfer printing technique that allows multiple patterned‐graphene transfers at desired locations is presented. Using the thermal‐expansion mismatch between the viscoelastic sacrificial layer and the elastic stamp, a “heating and cooling” process precisely positions patterned graphene layers on various substrates, including graphene prepatterns, hydrophilic surfaces, and superhydrophobic surfaces, with high transfer yields. A detailed theoretical analysis of underlying physics/mechanics of this approach is also described. The proposed transfer printing successfully integrates graphene‐based stretchable sensors, actuators, light‐emitting diodes, and other electronics in one platform, paving the way toward transparent and wearable multifunctional electronic systems.     

Interconnection Technology Based on InSn Solder for Flexible Display Applications

A novel interconnection technology based on a 52InSn solder was developed for flexible display applications. The display industry is currently trying to develop a flexible display, and one of the crucial technologies for the implementation of a flexible display is to reduce the bonding process temperature to less than 150°C. InSn solder interconnection technology is proposed herein to reduce the electrical contact resistance and concurrently achieve a process temperature of less than 150°C. A solder bump maker (SBM) and fluxing underfill were developed for these purposes. SBM is a novel bumping material, and it is a mixture of a resin system and InSn solder powder. A maskless screen printing process was also developed using an SBM to reduce the cost of the bumping process. Fluxing underfill plays the role of a flux and an underfill concurrently to simplify the bonding process compared to a conventional flip‐chip bonding using a capillary underfill material. Using an SBM and fluxing underfill, a 20 μm pitch InSn solder SoP array on a glass substrate was successfully formed using a maskless screen printing process, and two glass substrates were bonded at 130°C.     

A 12-b, 10-MHz, 250-mW CMOS A/D converter

A 12-b, 10-MHz, 250-mW, four-stage analog-to-digital converter (ADC) was implemented using a 0.8-μm p-well CMOS technology. The ADC based on a digitally calibrated multiplying digital-to-analog converter (MDAC) selectively employs a binary-weighted capacitor array in the front-end stage and a unit-capacitor array in the remaining back-end stages to obtain 12 b level linearity while maintaining high yield. All the analog and digital circuit functional blocks are fully integrated on a single chip, which occupies a die area of 15 mm² (4.2 mm×3.6 mm). Measured differential nonlinearity (DNL) and integral nonlinearity (INL) of the prototype are less than ±0.8 LSB and ±1.8 LSB, respectively