Fermentation of rice using amylolytic Bifidobacterium

Twenty-two amylolytic bifidobacteria grown in BHI-starch media were compared for the amylase activity of the intra- and extra-cellular enzymes. The activity of the cells grown in the liquid medium differed considerably. Among the strains tested B. adolescentis Int57 and B. adolescentis ZS8 exhibited higher activities than others. In rice medium containing 0.05% -cysteine·HCl and 0.2% yeast extract, the amylolytic Bifidobacterium strains grew considerably better than non-amylolytic Bifidobacterium strains. B. adolescentis Int57, which showed highest growth and amylase activity in the rice medium, was chosen and rice fermentation was investigated. The titratable acidity (TA) reached 2.43 and pH decreased to 4.4 after 24 h fermentation. The relative ratio of acetic acid to lactic acid gradually decreased during fermentation. The concentration of reducing sugar and amylase activity gradually increased and reached 14 mg maltose equivalent/ml and 35 mU/ml min, respectively, in 24 h. The accumulated reducing sugar was mostly maltotriose. The layer-separation of fermented product was stabilized by the addition of 1% gelatin. It was suggested that amylolytic bifidobacteria may be used for the production of fermented rice products.     

A Fully Integrated Thin‐Film Inductor and Its Application to a DC‐DC Converter

This paper presents a simple process to integrate thin‐film inductors with a bottom NiFe magnetic core. NiFe thin films with a thickness of 2 to 3 μm were deposited by sputtering. A polyimide buffer layer and shadow mask were used to relax the stress of the NiFe films. The fabricated double spiral thin‐film inductor showed an inductance of 0.49 μH and a Q factor of 4.8 at 8 MHz. The DC‐DC converter with the monolithically integrated thin‐film inductor showed comparable performances to those with sandwiched magnetic layers. We simplified the integration process by eliminating the planarization process for the top magnetic core. The efficiency of the DC‐DC converter with the monolithic thin‐film inductor was 72% when the input voltage and output voltage were 3.5 V and 6 V, respectively, at an operating frequency of 8 MHz.     

Efficient Generation of Scalable Transport Stream for High Quality Service in T‐DMB

We introduce an advanced terrestrial digital multimedia broadcasting (AT‐DMB) system that overcomes the limitation of data transmission rates of T‐DMB by doubling it with the same frequency bandwidth. In this letter, we propose an efficient algorithm which generates a scalable transport stream in AT‐DMB by multiplexing certain types of elementary streams encoded using scalable video coding and an MPEG‐surround audio coder for high‐quality multimedia services.     

Switched‐Capacitor Variable Gain Amplifier with Operational Amplifier Preset Technique

We present a novel operational amplifier preset technique for a switched‐capacitor circuit to reduce the acquisition time by improving the slewing. The acquisition time of a variable gain amplifier (VGA) using the proposed technique is reduced by 30% compared with a conventional one; therefore, the power consumption of the VGA is decreased. For additional power reduction, a programmable capacitor array scheme is used in the VGA. In the 0.13 μm CMOS process, the VGA, which consists of three‐stages, occupies 0.33 mm² and dissipates 19.2 mW at 60 MHz with a supply voltage of 1.2 V. The gain range is 36.03 dB, which is controlled by a 10‐bit control word with a gain error of ±0.68 LSB.     

Effects of Interfacial Dielectric Layers on the Electrical Performance of Top‐Gate In‐Ga‐Zn‐Oxide Thin‐Film Transistors

We investigate the effects of interfacial dielectric layers (IDLs) on the electrical properties of top‐gate In‐Ga‐Zn‐oxide (IGZO) thin film transistors (TFTs) fabricated at low temperatures below 200°C, using a target composition of In:Ga:Zn = 2:1:2 (atomic ratio). Using four types of TFT structures combined with such dielectric materials as Si₃N₄ and Al₂O₃, the electrical properties are analyzed. After post‐annealing at 200°C for 1 hour in an O₂ ambient, the sub‐threshold swing is improved in all TFT types, which indicates a reduction of the interfacial trap sites. During negative‐bias stress tests on TFTs with a Si3N4 IDL, the degradation sources are closely related to unstable bond states, such as Si‐based broken bonds and hydrogen‐based bonds. From constant‐current stress tests of Id = 3 µA, an IGZO‐TFT with heat‐treated Si₃N₄ IDL shows a good stability performance, which is attributed to the compensation effect of the original charge‐injection and electron‐trapping behavior.     

Phase-separated polydimethylsiloxane as a dielectric surface treatment layer for organic field effect transistors

We suggest a novel method for treating the surfaces of dielectric layers in organic field effect transistors (OFETs). In this method, a blend of poly(9,9-dioctylfluorene-alt-bithiophene) (F8T2) and dimethylsiloxane (DMS) with a curing agent is spin coated onto the surface of a dielectric substrate, silicon oxide (SiO₂), and then thermally cured. X-ray photoelectron spectroscopy, contact angle measurements, and morphology analysis were used to show that the hydrophilic DMS layer is preferentially adsorbed on the SiO₂ substrate during the spin coating process. After thermal curing, the bottom DMS layer becomes a hydrophobic PDMS layer. This bottom PDMS layer becomes thinner during curing due to the upward motion of the hydrophobic PDMS molecules. The FET mobility of the cured system was 10^?2 cm²/Vs, which is similar to that of polymeric semiconductors on octadecyltrichlorosilane treated SiO₂ dielectric layers. We also discuss the possibility of using this blend method to increase the air-stability of polymeric semiconductors.     

Low‐Power 512‐Bit EEPROM Designed for UHF RFID Tag Chip

In this paper, the design of a low‐power 512‐bit synchronous EEPROM for a passive UHF RFID tag chip is presented. We apply low‐power schemes, such as dual power supply voltage (VDD=1.5 V and VDDP=2.5 V), clocked inverter sensing, voltage‐up converter, I/O interface, and Dickson charge pump using Schottky diode. An EEPROM is fabricated with the 0.25 μm EEPROM process. Power dissipation is 32.78 μW in the read cycle and 78.05 μW in the write cycle. The layout size is 449.3 μm × 480.67 μm.     

Shorted Microstrip Patch Antenna Using Inductively Coupled Feed for UHF RFID Tag

A very small patch‐type RFID tag antenna (UHF band) using ceramic material mountable on metallic surfaces is presented. The size of the proposed tag is 25 mm×25 mm×3 mm. The impedance of the antenna can be easily matched to the tag chip impedance by adjusting the size of the shorting plate of the patch and the size of the feeding loop. The measured maximum reading distance of the tag at 910 MHz was 5 m when it was mounted on a 400 mm × 400 mm metallic surface. The proposed design is verified by simulation and measurements which show good agreement.     

Signal Synchronization Using a Flicker Reduction and Denoising Algorithm for Video‐Signal Optical Interconnect

A video signal through a high‐density optical link has been demonstrated to show the reliability of optical link for high‐data‐rate transmission. To reduce optical point‐to‐point links, an electrical link has been utilized for control and clock signaling. The latency and flicker with background noise occurred during the transferring of data across the optical link due to electrical‐to‐optical with optical‐to‐electrical conversions. The proposed synchronization technology combined with a flicker and denoising algorithm has given good results and can be applied in high‐definition serial data interface (HD‐SDI), ultra‐HD‐SDI, and HD multimedia interface transmission system applications.