A 3.3-V single power supply 16-Mb nonvolatile virtual DRAM using aNAND flash memory technology

A 3.3-V 16-Mb nonvolatile memory having operation virtually identical to DRAM with package pin compatibility has been developed. Read and write operations are fully DRAM compatible except for a longer RAS precharge time after write. Fast random access time of 63 ns with the NAND flash memory cell is achieved by using a hierarchical row decoder scheme and a unique folded bit-line architecture which also allows bit-by-bit program verify and inhibit operation. Fast page mode with a column address access time of 21 ns is achieved by sensing and latching 4 k cells simultaneously. To allow byte alterability, nonvolatile restore operation with self-contained erase is developed. Self-contained erase is word-line based, and increased cell disturb due to the word-line based erase is relaxed by adding a boosted bit-line scheme to a conventional self-boosting technique. The device is fabricated in a 0.5-μm triple-well, p-substrate CMOS process using two-metal and three-poly interconnect layers. A resulting die size is 86.6 mm², and the effective cell size including the overhead of string select transistors is 2.0 μm²     

A 120-mm2 64-Mb NAND flash memory achieving 180 ns/Byteeffective program speed

Emerging application areas of mass storage flash memories require low cost, high density flash memories with enhanced device performance. This paper describes a 64 Mb NAND flash memory having improved read and program performances. A 40 MB/s read throughput is achieved by improving the page sensing time and employing the full-chip burst read capability. A 2-μs random access time is obtained by using a precharged capacitive decoupling sensing scheme with a staggered row decoder scheme. The full-chip burst read capability is realized by introducing a new array architecture. A narrow incremental step pulse programming scheme achieves a 5 MB/s program throughput corresponding to 180 ns/Byte effective program speed. The chip has been fabricated using a 0.4-μm single-metal CMOS process resulting in a die size of 120 mm² and an effective cell size of 1.1 μm²     

Vertex-based inter-frame boundary encoding scheme

The boundary is approximated by a polygon which can be encoded with the smallest number of bits for maximum distortion. The temporal redundancy between two successive frames is efficiently removed with the proposed scheme, resulting in a lower bit rate than the conventional algorithms     

An 8-bit-resolution, 360-μs write time nonvolatile analog memorybased on differentially balanced constant-tunneling-current scheme(DBCS)

This paper describes a fast and accurate nonvolatile analog memory (NVAM) and its programming scheme. Both constant programming rate and single-pulse programmability have been achieved, which drastically enhance programming speed and accuracy. A prototype chip containing 8×128 NVAM cells (cell size of 9×13.6 μm²) has been fabricated using 0.8-μm CMOS. Each cell is measured to store more than eight bit levels within 360 μs     

Progressive NO2 Sensors with Rapid Alarm and Persistent Memory-Type Responses for Wide-Range Sensing Using Antimony Triselenide Nanoflakes

Antimony triselenide (Sb₂Se₃) nanoflake-based nitrogen dioxide (NO₂) sensors exhibit a progressive bifunctional gas-sensing performance, with a rapid alarm for hazardous highly concentrated gases, and an advanced memory-type function for low-concentration (<1 ppm) monitoring repeated under potentially fatal exposure. Rectangular and cuboid shaped Sb₂Se₃ nanoflakes, comprising van der Waals planes with large surface areas and covalent bond planes with small areas, can rapidly detect a wide range of NO₂ gas concentrations from 0.1 to 100 ppm. These Sb₂Se₃ nanoflakes are found to be suitable for physisorption-based gas sensing owing to their anisotropic quasi-2D crystal structure with extremely enlarged van der Waals planes, where they are humidity-insensitive and consequently exhibit an extremely stable baseline current. The Sb₂Se₃ nanoflake sensor exhibits a room-temperature/low-voltage operation, which is noticeable owing to its low energy consumption and rapid response even under a NO₂ gas flow of only 1 ppm. As a result, the Sb₂Se₃ nanoflake sensor is suitable for the development of a rapid alarm system. Furthermore, the persistent gas-sensing conductivity of the sensor with a slow decaying current can enable the development of a progressive memory-type sensor that retains the previous signal under irregular gas injection at low concentrations.     

Power Performance of AlGaN/GaN HEMTs Grown on SiC by Ammonia-MBE at 4 and 10 GHz

In this letter, we report on the microwave power and efficiency performance of AlGaN/GaN high-electron mobility transistors (HEMTs) grown by ammonia molecular beam epitaxy (ammonia-MBE) on SiC substrates. At 4 GHz, an output power density of 11.1 W/mm with an associated power-added efficiency (PAE) of 63% was measured at V _ds = 48 V on passivated devices. At 10 GHz, an output power density of 11.2 W/mm with a PAE of 58% was achieved for V _ds = 48 V. These results are the highest reported power performance for AlGaN/GaN HEMTs grown by ammonia-MBE and the first reported for ammonia-MBE on SiC substrates.     

Coplanar stripline resonators modeling and applications to filters

This paper presents coplanar stripline (CPS) resonators and their practical implementations to filters. Five types of CPS resonator are built using open and short-ended strips. Lumped-element equivalent circuits are presented for each resonator. Their performances are investigated and compared in terms of Q factor or bandwidth. Two types of bandpass filter are developed with the resonators. The bandpass filters have low-passband insertion losses and wide-stopband suppression bandwidths. Lumped-element equivalent circuits are presented for the bandpass filters. A wide-band CPS-to-microstrip transition is developed for the measurements. The back-to-back transition has an insertion loss of less than 3 dB and a return loss of better than 10 dB for the frequency range from 1.3 to 13.3 GHz (1:10.2)     

System reliability estimation using simulation combined with network reductions

This paper proposes a dynamic Monte Carlo sampling method, called the conditional minimal cut set (COMICS) algorithm, where all arcs are not simulated at each trial and all minimal cut sets need not be given in advance. The proposed algorithm repeats simulating a minimal cut set composed of the arcs which originate from the (new) source node and reducing the network on the basis of the states of simulated arcs until the s-t connectedness is confirmed. We develop the importance sampling estimator, the total hazard estimator and the hazard importance sampling estimator which are all based on the proposed algorithm, and compare the performance of these simulation estimators. It is found that these estimators can significantly reduce the variance of the raw simulation estimator and the usual importance sampling estimator.