A novel ternary half adder and multiplier based on carbon nanotube field effect transistors

A lot of research has been done on multiple-valued logic (MVL) such as ternary logic in these years. MVL reduces the number of necessary operations and also decreases the chip area that would be used. Carbon nanotube field effect transistors (CNTFETs) are considered a viable alternative for silicon transistors (MOSFETs). Combining carbon nanotube transistors and MVL can produce a unique design that is faster and more flexible. In this paper, we design a new half adder and a new multiplier by nanotechnology using a ternary logic, which decreases the power consumption and chip surface and raises the speed. The presented design is simulated using CNTFET of Stanford University and HSPICE software, and the results are compared with those of other studies.     

A computational and experimental investigation of the mechanical properties of single ZnTe nanowires

One-dimensional nanostructures such as ZnTe, CdTe, Bi(2)Te(3) and others have attracted much attention in recent years for their potential in thermoelectric devices among other applications. A better understanding of their mechanical properties is important for the design of devices. A combined experimental and computational approach has been used here to investigate the size effects on the Young's modulus of ZnTe nanowires (NWs). The mechanical properties of individual ZnTe nanowires in a wide diameter range (50-230 nm) were experimentally measured inside a high resolution transmission electron microscope using an atomic force microscope probe with the ability to record in situ continuous force-displacement curves. The in situ observations showed that ZnTe NWs are flexible nanostructures with the ability to withstand relatively high buckling forces without becoming fractured. The Young's modulus is found to be independent of nanowire diameter in the investigated range, in contrast to reported results for ZnO NWs and carbon nanotubes where the modulus increases with a decrease in diameter. Molecular dynamics simulations performed for nanowires with diameters less than 20 nm show limited size dependence for diameters smaller than 5 nm. The surface atoms present lower Young's modulus according to the simulations and the limited size dependency of the cylindrical ZnTe NWs is attributed to the short range covalent interactions.     

Ultra-area-efficient reversible multiplier

One of the most promising technologies in designing low-power circuits is reversible computing. It is used in nanotechnology, quantum computing, quantum dot cellular automata (QCA), DNA computing, optical computing and in CMOS low-power designs. Because of this broad range of applications, extensive works have been proposed in constructing reversible gates and reversible circuits, including basic universal logic gates, adders and multipliers.In this paper we have highlighted the design of reversible multipliers and have presented two designs. Integration of adder circuit and multiplier in the design is described, in order to utilize the unused capacity of the multipliers.We have achieved reduction in quantum cost compared to similar designs as well as appending the adder circuit to the multiplier which leads to better usage of resources. Additionally, we have described the multiplier problem for implementing n×n reversible multiplier and analyzed the required resources in terms of n. Practical implementation of this design can be achieved with the existing technologies in CMOS and nanotechnology.Lastly, we make a tradeoff between area and time complexity to obtain two designs which can be used in different situations where different requirements are of different importances. We compare the proposed designs with each other and also to the existing ones.     

High-Performance Mixed-Mode Universal Min-Max Circuits for Nanotechnology

In this paper a low-power, high-speed and high-resolution voltage-mode Min-Max circuit, as well as a new efficient universal structure for determining the minimum and maximum values of the input digital signals, is proposed for nanotechnology. In addition, the proposed designs provide rail-to-rail input and output signals which enhance the performance and the robustness of the circuits. The advantage of the proposed Min-Max circuit is that it is extendable for any arbitrary n-digit and radix-r input numbers. Comprehensive simulation results at CMOS and CNFET technologies demonstrate the low-power and high-performance operation as well as insusceptibility to PVT variations of the proposed structure.     

Cooperative multiple relay system for frequency selective environment: outage analysis and power allocation

In this paper, we propose a novel cooperative relaying scheme with multiple relays for frequency selective wireless environment. In our proposed scheme, the frequency selective wireless channel is divided into flat fading sub‐channels. Cooperative relaying is then employed over each sub‐channel to improve the system diversity order. We then investigate the asymptotic behavior of the outage probability and show that the proposed scheme achieves full diversity order in both amplify and forward (AF) and adaptive decode and forward (ADF) relaying scenarios. Furthermore, we propose a power allocation strategy to minimize the system outage probability. Simulation results confirm our analysis and show that the proposed power allocation method outperforms uniform power allocation. Copyright © 2010 John Wiley & Sons, Ltd.     

Energy and Exergy Analyses of Thin-Layer Drying of Potato Slices in a Semi-Industrial Continuous Band Dryer

This article is concerned with the energy and exergy analyses of the continuous-convection drying of potato slices. The first and second laws of thermodynamics were used to calculate the energy and exergy. A semi-industrial continuous-band dryer has been designed and used for drying experiments. The equipment has a drying chamber of 2 m length and the inlet air used for drying is heated by gas power. The experiments were conducted on potato slices with thickness of 5 mm at three different air temperatures of 50, 60 and 70°C, drying air mass flow rates of 0.61, 1.22, and 1.83 kg/s and feeding rates of 2.31 × 10^?4, 2.78 × 10^?4, and 3.48 × 10^?4 kg/s. The energy utilization and energy utilization ratio were found to vary between 3.75 and 24.04 kJ/s and 0.1513 and 0.3700, respectively. These values show that only a small proportion of the supplied energy by the heater was used for drying. The exergy loss and exergy efficiency were found to be in the range of 0.5987 to 13.71 kJ/s and 0.5713 to 0.9405, respectively, indicating that the drying process was thermodynamically inefficient and much energy was vented in the exhaust air. In addition, the results showed that the feeding rate and the temperature and flow rate of the drying air had an important effect on energy and exergy use. This knowledge will provide insights into the optimization of a continuous dryer and the operating parameters that causes reduction of energy consumption and losses in continuous drying.     

Differential Cascode Voltage Switch (DCVS) Strategies by CNTFET Technology for Standard Ternary Logic

Differential Cascode Voltage Switch (DCVS) is a well-known logic style, which constructs robust and reliable circuits. Two main strategies are studied in this paper to form static DCVS-based standard ternary fundamental logic components in digital electronics. While one of the strategies leads to fewer transistors, the other one has higher noise margin. New designs are simulated with HSPICE and 32 nm CNTFET technology at various realistic conditions such as different power supplies, load capacitors, frequencies, and temperatures. Simulations results demonstrate their robustness and efficiency even in the presence of PVT variations. In addition, new noise injection circuits for ternary logic are also presented to perform noise immunity analysis.     

A new quantum-dot cellular automata full-adder

A novel expandable five-input majority gate for quantum-dot cellular automata and a new full-adder cell are presented. Quantum-dot cellular automata (QCA) is an emerging technology and a possible alternative for semiconductor transistor based technologies. A novel QCA majority-logic gate is proposed. This component is suitable for designing QCA circuits. The gate is simple in structure and powerful in terms of implementing digital functions. By applying these kinds of gates, the hardware requirement for a QCA design can be reduced and circuits can be simpler in level, gate counts and clock phases. In order to verify the functionality of the proposed device, some physical proofs are provided. The proper functionality of the FA is checked by means of computer simulations using QCADesigner tool. Both simulation results and physical relations confirm our claims and its usefulness in designing every digital circuit.     

Polyionene/Br3 Grafted on Magnetic Nanoparticles as an Efficient and Eco-Friendly Catalyst for the Metal Free Synthesis of 3,4-Dihydropyrimidin-2(1H)-Ones/Thiones

Silicon - A novel polyionene modified magnetic nanoparticle with a core-shell-shell structure was developed for utilization as a heterogeneous catalyst in the metal free synthesis of...