Trajectory design considering derivative of jerk for head-positioning of disk drive system with mechanical vibration

In this paper, we propose a novel design method of target trajectory for high-speed and high-precision head positioning of a hard disk drive (HDD) system. To realize smooth acceleration and deceleration, the derivative of jerk is considered not to activate any mechanical vibrations. We applied the well-known optimal control theory to fix the initial and terminal conditions. Moreover, we show that various performances can be improved by introducing time-varying weighting coefficients. Some experimental results using a 2.5-in HDD are shown to verify the effectiveness of the proposed method.     

Effect of ohmic contacts on buffer leakage of GaN transistors

The effect of ohmic contacts on the buffer leakage of GaN transistors is presented. The buffer leakage for AlGaN/GaN high-electron mobility transistors and GaN MESFETs grown on the same underlying buffer was observed to be different. Controlled experiments show that the increased buffer leakage is due to the nature of the alloyed ohmic contacts and can be minimized if they are screened by the Si doping or by the two-dimensional electron gas.     

Transient thermal analysis of sapphire wafers subjected to thermal shocks

Rapid heating and cooling are commonly encountered events in integrated circuit processing, which produce thermal shocks and consequent thermal stresses in wafers. The present paper studies the heat transfer in sapphire wafers during a thermal shock as well as the dependence of the wafer temperature on various process parameters. A three-dimensional finite-element model of a single sapphire wafer was developed to analyze the transient heat conduction in conjunction with the heat radiation and heat convection on the wafer surfaces. A silicon wafer was also investigated, for comparison. It was found that the rapid thermal loading leads to a parabolic radial temperature distribution, which induces thermal stresses even if the wafer is not mechanically restrained. The study predicted that for sapphire wafers the maximum furnace temperature of 800 /spl deg/C should be held for two hours in order to get a uniform temperature throughout the wafer.     

Comprehensive Study of Emitter-Ledge Thickness of InGaP/GaAs HBTs

A comprehensive study of emitter-ledge thickness of InGaP/GaAs heterojunction bipolar transistors (HBTs) has been undertaken. It is shown that the recombination rate and electron densities are drastically increased near the exposed base surface between the base contact and the emitter ledge. In contrast, the corresponding hole densities are decreased. If the emitter ledge is too thick, current will flow through the undepleted ledge, which increases the emitter-size effect. In contrast, if the emitter ledge is too thin, it may not effectively passivate the surface. Therefore, the thickness of the emitter ledge is a crucial issue and should be carefully considered. It is shown that, from simulated and experimental results, the optimum emitter-ledge thickness of InGaP/GaAs HBT is 100-200 Aring     

Design of Ultra-Wideband Monopulse Receiver

In this paper, we propose a novel amplitude-comparison monopulse receiver architecture for ultra-wideband radars. This monopulse receiver consists of four ridged-horn antennas placed in a square-feed configuration, a comparator circuit that generates the monopulse sum and difference signals, cross-correlation receivers that detect the monopulse signals, and an amplitude-comparison monopulse processor that determines the target's angular position. The derived monopulse sum and difference signals are verified through measurements. The derived sum and difference patterns are compared with measured patterns, and they show good agreements-measured 3-dB beamwidth=6.4deg(derived=6deg), measured unambiguous tracking range=plusmn5deg(derived=plusmn5deg), and measured sum pattern sidelobe level=-6 dB (derived=-8 dB)     

Advances in Vapor Pressure Modeling for Electronic Packaging

Two advanced techniques have been developed for modeling vapor pressure within the plastic IC packages during solder reflow. The first involves the extension of the "wetness" technique to delamination along multimaterial interface and during dynamic solder reflow. Despite its simplicity, this technique is capable of offering reliable and accurate prediction for packages with high flexural rigidity. For packages with low flexural rigidity, the new "decoupling" technique that integrates thermodynamics, moisture diffusion, and structural analysis into a unified procedure has been shown to be more useful. The rigorous technique has been validated on both leadframe-based as well as laminate-based packages. With high accuracy and computational efficiency, these dynamic modeling tools will be valuable for optimization of package construction, materials, and solder reflow profile against popcorn cracking for both SnPb and Pb-free solders     

Exposed Die-Top Encapsulation Molding for an Improved High- Performance Flip Chip BGA Package

The recent advancement in high- performance semiconductor packages has been driven by the need for higher pin count and superior heat dissipation. A one-piece cavity lid flip chip ball grid array (BGA) package with high pin count and targeted reliability has emerged as a popular choice. The flip chip technology can accommodate an I/O count of more than five hundreds500, and the die junction temperature can be reduced to a minimum level by a metal heat spreader attachment. None the less, greater expectations on these high-performance packages arose such as better substrate real estate utilization for multiple chips, ease in handling for thinner core substrates, and improved board- level solder joint reliability. A new design of the flip chip BGA package has been looked into for meeting such requirements. By encapsulating the flip chip with molding compound leaving the die top exposed, a planar top surface can be formed. A, and a flat lid can then be mounted on the planar mold/die top surface. In this manner the direct interaction of the metal lid with the substrate can be removed. The new package is thus less rigid under thermal loading and solder joint reliability enhancement is expected. This paper discusses the process development of the new package and its advantages for improved solder joint fatigue life, and being a multichip package and thin core substrate options. Finite-element simulations have been employed for the study of its structural integrity, thermal, and electrical performances. Detailed package and board-level reliability test results will also be reported     

Operation of HTS Toggle-Flip-Flop Circuit With Improved Layout Design

Toggle-flip-flop (T-FF) is one of the most important high-T_c superconducting single-flux quantum (HTS SFQ) circuit components and has been designed and fabricated by using YBa₂Cu₃ O_7-delta ramp-edge junction technology. The circuit layout of the T-FF was improved to suppress the junction critical current (I_c) spread in the circuit. Test circuits, which include a T-FF with a single output for evaluating the logic operation and measuring the operating frequency, were fabricated and their operation characteristics were investigated. The T-FF circuit with a single output was successfully operated and finite direct current (dc) supply current margins were obtained at temperatures from 27 to 34 K. Moreover, the maximum operating frequency of the T-FF was estimated to be 360 GHz at 4.2 K and 114 GHz at 41 K. In addition, reduction of dc supply current margins due to thermal noise was also investigated. According to the numerical simulation in which parasitic inductances were taken into account, the narrowest margin in the T-FF circuit wider than plusmn10% was maintained with a bit-error rate (BER) of 10^-6 up to 40 K     

Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems

This paper introduces a new family of low-power and high-performance flip-flops, namely conditional data mapping flip-flops (CDMFFs), which reduce their dynamic power by mapping their inputs to a configuration that eliminates redundant internal transitions. We present two CDMFFs, having differential and single-ended structures, respectively, and compare them to the state-of-the-art flip-flops. The results indicate that both CDMFFs have the best power-delay product in their groups, respectively. In the aspect of power dissipation, the single-ended and differential CDMFFs consume the least power at data activity less than 50%, and are 31% and 26% less power than the conditional capture flip-flops at 25% data activity, respectively. In the aspect of performance, CDMFFs achieve small data-to-output delays, comparable to those of the transmission-gate pulsed latch and the modified-sense-amplifier flip-flop. In the aspect of timing reliability, CDMFFs have the best internal race immunity among pulse-triggered flip-flops. A post-layout case study is demonstrated with comparison to a transmission-gate flip-flop. The results indicate the single-ended CDMFF has 34% less in data-to-output delay and 28% less in power at 25% data activity, in spite of the 34% increase in size     

An investigation into the effects of probing and wire bonding stress on the reliability of BOAC

This work describes two types of low stress bonding over active circuit (BOAC) structures applying a finite element analysis. The advantage of improving the chip area utility of the BOAC design is approximately 150–180 μm for each dimension. A 0.13 μm 2 Mb high-speed SRAM with fluorinated silicate glass (FSG) low-k dielectric was combined with these two BOAC structures as the test vehicles to evaluate the impact of the probing and wire bonding stress on the reliability. Initially, a cantilevered probe card was applied to probe the BOAC pads using the typical and the worse probing conditions. Before and after the circuits probing (CP1 and CP2) the experimental results were compared, including the 2 Mb high-speed SRAM yield and wafer bit map data. The difference between the CP1 and CP2 results were negligible for all probing split cells. Next, the cross-section of the BOAC pad under the probing area was investigated following the worst probing condition. In addition, the BOAC pads evaluate the bondability, including the use of ball shear, wire pull and cratering tests. Moreover, all BOAC packaging samples underwent reliability tests, including HTOL, TCT, TST, and HTST. All the bondability and reliability tests passed the criteria for both proposed BOAC structures. Finally, the immunity level of both proposed BOAC pads, for ESD-HBM (human body mode) and ESD-MM (machine mode), differed slightly from the normal pads. No performance degradation was detected. Accordingly, this work shows that both proposed BOAC structures can be used to improve the active chip area utility or save the chip area.