Enhanced microstrip filter design with a uniform dielectric overlay for suppressing the second harmonic response

Parallel-coupled microstrip filters are designed to suppress spurious response at twice the passband frequency (2f/sub o/) with a uniform dielectric overlay. The overlay dielectric is used to equalize the modal phase velocities of each coupled stage. Based on the method, we have a large degree of freedom in choosing thickness and permittivity of the overlay dielectric. The image impedances of all the coupled stages in such a filter need adjusting to complete the filter synthesis. Two filters are fabricated and measured results show a good agreement with the simulation. A suppression of at least 40 dB to the spurious responses at 2f/sub o/ is achieved.     

A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices

This paper extends the timing test model in [5] to be more realistic by including the effects of the test fixtures between a device under test and a tester. The paper enables analyzing the trade-offs that arise between the predicted yield and the required overall test environment timing accuracy (OTETA) which involves the tester overall timing accuracy (OTA) and the test fixtures' impacts. We specifically focus on the application of the extended model to predict the test yield of standard high-speed interconnects, such as PCI Express, Parallel/Serial RapidIO, and HyperTransport. The extended model reveals that achieving an actual yield of 80% with a test escape of 300 DPM (Defects Per Million) requires an equivalent OTETA that is about half the acceptable absolute limit of the tested parameter. Baosheng Wang received his B.S. degree from Beijing University of Aeronautics and Astronautics (BUAA), Beijing, P.R. China, in 1997 and M.S. degree from Precision Instrument & Mechanical Engineering from the Tsinghua University, Beijing, P. R. China in 2000. In 2005, he received his Ph.D. degree in Electrical Engineering from the University of British Columbia (UBC), Vancouver, BC, Canada. During his Master study, he was doing MEMS, Micro Sensors and Digital Signal processing. From 2000 to 2001, he worked in Beijing Gaohong Telecommunications Company as a hardware engineer in ATM technology. Currently, he is a Design-for-Test (DFT) engineer at ATI Technologies Inc., Markham, Ontario, Canada. He publishes widely at international conferences and journals. His primary research interests are time-driven or timing-oriented testing methodologies for System on-a-Chip (SoC). These fields include test time reduction for SRAMs, accelerated reliability test for non-volatile memories, yield analysis for SoC timing tests, SoC path delay timing characterization and embedded timing measurements. Andy Kuo is currently a Ph.D student of System on a Chip (SoC) Research Lab at the Department of Electrical and Computer Engineering, University of British Columbia. He received his M.A.Sc. and B.A.Sc in electrical and computer engineering from University of British Columbia and University of Toronto in 2004 and 2002 respectively. His research interests include high-speed signal integrity issues, jitter measurement, serial communications. Touraj Farahmand received the B.Sc. degree in Electrical Engineering from Esfahan University of Technology, Esfahan, Iran in 1989 and the M.Sc. in Control Engineering from Sharif university of Technology, Tehran, Iran in 1992. After graduation, he joined the Electrical and Computer Research center of Esfahan University of Technology where he was involved in the DSP algorithm development and design and implementation of the control and automation systems. Since October 2001, he has been working in the area of high-speed signal timing measurement at SoC (System-on-a-Chip) lab of UBC (University of British Columbia) as a research engineer. His research interests are signal processing, jitter measurement, serial communication and control. André Ivanov is Professor in the Department of Electrical and Computer Engineering, at the University of British Columbia. Prior to joining UBC in 1989, he received his B.Eng. (Hon.), M. Eng., and Ph.D. degrees in Electrical Engineering from McGill University. In 1995–96, he spent a sabbatical leave at PMC-Sierra, Vancouver, BC. He has held invited Professor positions at the University of Montpellier II, the University of Bordeaux I, and Edith Cowan University, in Perth, Australia. His primary research interests lie in the area of integrated circuit testing, design for testability and built-in self-test, for digital, analog and mixed-signal circuits, and systems on a chip (SoCs). He has published widely in these areas and holds several patents in IC design and test. Besides testing, Ivanov has interests in the design and design methodologies of large and complex integrated circuits and SoCs. Dr. Ivanov has served and continues to serve on numerous national and international steering, program, and/or organization committees in various capacities. Recently, he was the Program Chair of the 2002 VLSI Test Symposium (VTS'02) and the General Chair for VTS'03 and VTS'04. In 2001, Ivanov co-founded Vector 12, a semiconductor IP company. He has published over 100 papers in conference and journals and holds 4 US patents. Ivanov serves on the Editorial Board of the IEEE Design and Test Magazine, and Kluwer's Journal of Electronic Testing: Theory and Applications. Ivanov is currently the Chair of the IEEE Computer Society's Test Technology Technical Council (TTTC). He is a Golden Core Member of the IEEE Computer Society, a Senior Member of the IEEE, a Fellow of the British Columbia Advanced Systems Institute and a Professional Engineer of British Columbia. Yong Cho received the B.S. degree from Kyung Pook National Unviersity, Korea, in 1981 and the M.S. degree from in electrical and computer engineering from the University of South Carolina, Columbia, S.C., in 1988 and the Ph.D. degree in electrical engineering and applied physics from Case Western Reserve University, Cleveland, OH, in 1992. He is currently a Professor with the Department of Electronics Engineering, Konkuk University, Seoul, Korea. His recent research interests include SoC Design and Verification, H/W and S/W co-design, and embedded programming on SoC. Sassan Tabatabaei received his PHD in Electrical Engineering from the University of British Columbia, Vancouver, Canada in 2000. Since then, he has held several senior technical positions at Vector12 Corp, Guide Technology, and Virage Logic. His professional and research interests include mixed-signal design and test, and signal integrity and jitter test methodologies for high-speed circuits and multi-Gbps serial interfaces. He has published several papers and holds a US patent in the area of timing and jitter measurement. Currently, he holds the position of the director for embedded test at Virage Logic Corporation.     

Joint connection-level and packet-level quality-of-service support for VBR traffic in wireless multimedia networks

In this paper, we investigate call admission control (CAC) schemes that can jointly provide connection-level quality-of-service (QoS) (in terms of the new call blocking probability and the handoff dropping probability) and packet-level QoS (in terms of the packet loss probability) for wireless multimedia networks. Stationary CAC schemes are proposed as the results of the solution to constrained optimization problems. A dynamic CAC scheme that can be adapted to varied and varying traffic conditions dynamically is also proposed. The proposed CAC schemes are computationally efficient and easy to implement, thus being suitable for real-time system deployment. Simulation results have demonstrated that the proposed dynamic CAC scheme achieves better performance when applied to realistic traffic conditions found in wireless multimedia networks.     

A BiCMOS dynamic multiplier using Wallace tree reductionarchitecture and 1.5-V full-swing BiCMOS dynamic logic circuit

The authors present a BiCMOS dynamic multiplier, which is free from race and charge-sharing problems, using Wallace tree reduction architecture and 1.5-V full-swing BiCMOS dynamic logic circuit. Based on a 1-μm BiCMOS technology, a 1.5-V 8×8 multiplier designed, shows a 2.3× improvement in speed as compared to the CMOS static one     

激光光斑探测系统软件设计与分析

对激光光斑探测系统构成和光斑探测原理进行分析研究。在激光光斑探测系统软件设计中对图像采集控制和图像显示提出了全新的控制手段和设计思路,并对激光光斑采集软件和图像处理软件进行了详细设计说明,在图像处理软件设计中运用了一种激光光斑能量分布的三维伪彩色可视化方法,更加清晰反应光斑的不同区域能量分布的相对大小和位置。     

Gold Nanoparticles and g‐C3N4‐Intercalated Graphene Oxide Membrane for Recyclable Surface Enhanced Raman Scattering

Toxic organic pollutants in the aquatic environment cause severe threats to both humans and the global environment. Thus, the development of robust strategies for detection and removal of these organic pollutants is essential. For this purpose, a multifunctional and recyclable membrane by intercalating gold nanoparticles and graphitic carbon nitride into graphene oxide (GNPs/g‐C₃N₄/GO) is fabricated. The membranes exhibit not only superior surface enhanced Raman scattering (SERS) activity attributed to high preconcentration ability to analytes through π–π and electrostatic interactions, but also excellent catalytic activity due to the enhanced electron–hole separation efficiency. These outstanding properties allow the membrane to be used for highly sensitive detection of rhodamine 6G with a limit of detection of 5.0 × 10^?14m and self‐cleaning by photocatalytic degradation of the adsorbed analytes into inorganic small molecules, thus achieving recyclable SERS application. Furthermore, the excellent SERS activity of the membrane is demonstrated by detection of 4‐chlorophenol at less than nanomolar level and no significant SERS or catalytic activity loss was observed when reusability is tested. These results suggest that the GNPs/g‐C₃N₄/GO membrane provides a new strategy for eliminating traditional, single‐use SERS substrates, and expands practical SERS application to simultaneous detection and removal of environmental pollutants.     

Fault diagnosis in reconfigurable VLSI and WSI processor arrays

A systematic efficient fault diagnosis method for reconfigurable VLSI/WSI array architectures is presented. The basic idea is to utilize the output data path independence among a subset of processing elements (PEs) based on the topology of the array under test. The divide and conquer technique is applied to reduce the complexity of test application and enhance the controllability and observability of a processor array. The array under test is divided into nonoverlapping diagnosis blocks. Those PEs in the same diagnosis block can be diagnosed concurrently. The problem of finding diagnosis blocks is shown equivalent to a generalizedEight Queens problem. Three types of PEs and one type of switches, which are designed to be easily testable and reconfigurable, are used to show how to apply this approach. The main contribution of this paper is an efficient switch and link testing procedure, and a novel PE fault diagnosis approach which can speed up the testing by at leastO(V^1/2) for the processor arrays considered in this paper, where V is the number of PEs. The significance of our approach is the ability to detect as well as to locate multiple PE, switch, and link faults with little or no hardware overhead.     

An overview of manufacturing yield and reliability modeling forsemiconductor products

This paper presents an overview of yield, reliability, burn-in, cost factors, and fault coverage as practiced in the semiconductor manufacturing industry. Reliability and yield modeling can be used as a foundation for developing effective stress burn-in, which in turn can warranty high-quality semiconductor products. Yield models are described and their advantages and disadvantages are discussed. Both yield reliability relationships and relation models between yield and reliability are thoroughly analyzed in regard to their importance to semiconductor products     

基于概率逼近的本原BCH码编码参数的盲识别方法

针对本原BCH码编码参数的盲识别问题,该文提出了一种基于概率逼近的盲识别方法。首先,利用Gauss分布和Poisson分布逼近随机码字的根概率特性,确定了搜索BCH码长的门限;然后,通过分析本原域元素的检错能力及同构对域的影响,应用临近域对的方法确定编码域,提高了其识别能力;最后,给出识别生成多项式时的共轭根系表,从而减少了计算量。仿真结果表明,在较高的误码率下,该方法能快速地识别出BCH码编码所采用的编码参数。     

GaAsSb/InAlAs PA DHBTs Grown by Production MBE

The epi material growth of GaAsSb based DHBTs with InAlAs emitters are investigated using a 4 × 100mm multi-wafer production Riber 49 MBE reactor fully equipped with real-time in-situ sensors including an absorption band edge spectroscope and an optical-based flux monitor. The state-of-the-art hole mobilities are obtained from 100nm thick carbon-doped GaAsSb. A Sb composition variation of less than ± 0.1 atomic percent across a 4 × 100mm platen configuration has been achieved. The large area InAlAs/GaAsSb/InP DHBT device demonstrates excellent DC characteristics,such as BVCEO＞6V and a DC current gain of 45 at 1kA/cm2 for an emitter size of 50μm × 50μm. The devices have a 40nm thick GaAsSb base with p-doping of 4. 5 × 1019cm-3 . Devices with an emitter size of 4μm × 30μm have a current gain variation less than 2% across the fully processed 100mm wafer. ft and fmax are over 50GHz,with a power efficiency of 50% ,which are comparable to standard power GaAs HBT results. These results demonstrate the potential application of GaAsSb/InP DHBT for power amplifiers and the feasibility of multi-wafer MBE for mass production of GaAsSb-based HBTs.