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101.
A novel wireless local-area network (WLAN) chip antenna suitable to be mounted above the system ground plane of a mobile device is presented. The antenna in the study is easily fabricated from folding a single metal plate onto a foam base, and mainly comprises a short-circuited radiating strip and an antenna ground. The antenna ground occupies the bottom surface and two adjacent side surfaces of the foam base. When the antenna is mounted at the corner of the system ground plane, this antenna ground structure is expected to effectively reduce the antenna's possible fringing electromagnetic fields inside the mobile device. In this case, when the associated element such as the radio-frequency shielding metal case is placed under the proposed antenna, small or negligible variations in the antenna performance are obtained. Design considerations of the proposed antenna for WLAN operation in the 2.4 GHz band are described, and results of the constructed prototypes are presented.  相似文献   
102.
Microlens arrays are introduced on glass substrates to improve the out-coupling efficiency of organic light-emitting devices (OLEDs). The microlenses suppress waveguiding loss in the substrate. A theoretical model, based on electromagnetic wave propagation and geometric ray tracing, is developed to simulate the enhancement effects and optimize the structure parameters of the lens pattern. A simple soft-lithography approach is employed to fabricate the microlens array on glass substrates. With the use of an optimized lens pattern, an increase of over 85% in the coupling efficiency of the OLED is expected theoretically. An increase of 70% in the coupling efficiency is achieved experimentally, without detrimental effect to the electrical performance of the OLED.  相似文献   
103.
玻璃衬底上MIUC Poly-Si TFT显示驱动电路   总被引:4,自引:0,他引:4       下载免费PDF全文
以高性能的金属诱导单一方向横向晶化多晶硅薄膜晶体管(MIUC poly-Si TFT)为基础,研制出性能能满足AM-LCD和AM-OLED要求、版图和象素尺寸适配、制备工艺和象素电路兼容的多晶硅TFT行扫描和列驱动电路.该行扫描电路工作电压为3.5-10V;当工作电压为5V、负载电容为22pf时,下降沿约为150ns,上升沿约为205ns,最高工作频率在1MHz以上;列驱动电路工作电压为3.5-8V;当工作电压为5V、负载电容为22pf时,上升沿约为200ns,信号衰减率为15%(64μs扫描周期),最高工作频率达到4MHz.将该MIUC poly-Si TFT多晶硅行扫描、列驱动电路和有源选址电路集成到同一基板上,制备出象素数为80×RGB×60、动态显示效果良好的全集成型LCD屏样品.  相似文献   
104.
Characterization and modeling of on-chip spiral inductors for Si RFICs   总被引:4,自引:0,他引:4  
The paper presents a complete characterization of on-chip inductors fabricated in BiCMOS technology. First, a study of the scaling effect of inductance on geometry and structure parameters is presented to provide a clear guideline on inductor scaling with suitable quality factors. The substrate noise analysis and noise reduction techniques are then investigated. It is shown that floating well can improve both quality factor and noise elimination by itself under 3 GHz and together with a guard ring above 3 GHz. Finally, for accurate circuit simulations, a new inductor model is developed for predicting the skin effect and eddy effect and associated quality factor and inductance.  相似文献   
105.
The performance of an innovative delta-doped AlGaN/AlN/GaN heterojunction field-effect transistor (HFET) structure is reported. The epitaxial heterostructures were grown on semi-insulating SiC substrates by low-pressure metalorganic chemical vapour deposition. These structures exhibit a maximum carrier mobility of 1058 cm2/V s and a sheet carrier density of 2.35×1013 cm-2 at room temperature, corresponding to a large ns μn product of 2.49×1016 V s. HFET devices with 0.25 μm gate length were fabricated and exhibited a maximum current density as high as 1.5 A/mm (at VG=+1 V) and a peak transconductance of gm=240 mS/mm. High-frequency device measurements yielded a cutoff frequency of ft≃50 GHz and maximum oscillation frequency fmax≃130 GHz  相似文献   
106.
This paper presents a high performance RF CMOS technology with a complete portfolio of RF and base band components for single-chip systems. Using an optimized 0.13 μm CMOS topology, fT of 86 GHz and fmax of 73 GHz are obtained, in addition to a NFmin of 1.5 dB without ground-shielded signal pad. The high-Q accumulation-mode and diode varactors are optimized to perform a high tuning range of 47% and 25%, respectively. Inductors with a quality factor of 18 at 1.7 nH are obtained using copper interconnect, while capacitors with high unit capacitance and quality factor are fabricated with metal-insulator-metal structures. Finally, a deep n-well isolation is adopted to suppress the interblock coupling noise penetrating through substrate by 40 and 25 dB at 0.1 and 2.4 GHz, respectively. These results clearly demonstrate that CMOS technology can provide a complete solution for single-chip wireless systems.  相似文献   
107.
The kinetic behavior of the Pd/In bilayer reaction is analyzed, with emphasis on the effect of nanometer-scale diffusion barriers at the Pd/In interface. It is shown that the Pd/In reaction proceeds rapidly and without a discernable incubation period at temperatures below 200 C if the Pd/In interface is nominally free of either contamination or intentionally-deposited intervening layers. Air exposure of the Pd surface prior to In deposition is sufficient to delay the onset of the reaction to produce the intermetallic phase by PdIn3 for several minutes at 200 C. This incubation period can be further controlled by deposition of a nanometer-scale Ti layer onto the Pd prior to air exposure and In deposition. The implications of these results for the design of transient-liquid-phase waferbonding processes based on Pd−In are discussed.  相似文献   
108.
The DC pulse hot-carrier-stress effects on the degradation in gate-induced drain leakage (GIDL) current in nMOSFETs in a high field regime and the mechanisms of stress-induced degradation are studied. In this paper, we investigate DC pulse stress parameters in GIDL which include frequency, rise/fall time, and stressing pulse amplitude. The contributions of hot-hole injection, interface state generation, and hot-electron injection in a period of transient stress are identified. It is found that the device degradation increases with increased pulse frequency under maximum gate current stress, while it decreases with reduced pulse frequency under maximum substrate current stress. This work is useful for DC pulse hot-carrier-stress reliability analysis under circuit operation  相似文献   
109.
Shunt-connected trilevel power inverter in three-phase four-wired system as an active filter or individual current supply (peak-load supply) is studied by a novel technique: three-dimensional (3-D) voltage vectors pulse width modulation (PWM). In past decades, almost all the study for PWM is limited to the two-dimensional (2-D) domain, α and β frames, in a three-phase three-wired system. However, in practical operation, there are many three-phase four-wired systems in distribution sites. The generalized study of 3-D two-level and three-level inverters is achieved in this paper so as to perform the basic theory of 3-D multilevel space vector switching PWM technique. The sign cubical hysteresis control strategy is proposed and studied with simulation results in 3-D aspect. The 3-D PWM technique in three-level inverters is accomplished  相似文献   
110.
Addresss the problem of designing polarization-insensitive Bragg gratings in zero-birefringence ridge waveguides. It is known that the reflection spectrum of a Bragg grating is be polarization-independent if both the phase-matching condition and the coupling coefficient are polarization-independent. While the use of a zero-birefringence waveguide can guarantee a polarization-independent phase-matching condition, it does not in general lead to a polarization-independent coupling coefficient. Our theoretical analysis indicates, however, that a strictly polarization-independent coupling coefficient is not essential for the achievement of a polarization-insensitive Bragg grating. Our detailed calculations on both corrugation and phase gratings in zero-birefringence ridge waveguides reveal some general design principles. Our results should be useful for the design of a wide range of Bragg-grating-based waveguide devices  相似文献   
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