A power model for routers: modeling Alpha 21364 and InfiniBand routers

As interconnection networks proliferate to many new applications, a low-latency high-throughput fabric no longer suffices. An architectural-level power model for interconnection network routers will let researchers and designers easily factor in power when exploring architectural tradeoffs.     

Guest Editors' Introduction: Tackling Key Problems in NoCs

This special issue highlights recent innovations in network on a chip (NoC) design. The four articles fall into two main thrusts: the first three focus on design methodology challenges in NoCs; the final article demonstrates a practical case study implementation of an NoC.     

Efficient phosphorescent white organic light-emitting devices incorporating blue iridium complex and multifunctional orange–red osmium complex

By using the unique properties of the efficient orange–red phosphorescent osmium complex in combination with an efficient blue phosphorescent Iridium complex, efficient white organic light-emitting devices with forward viewing efficiencies up to (17% photon/electron, 36 cd/A, 28 lm/W) and white organic light-emitting devices with color stability vs. brightness can be implemented. Results show that the osmium complex is a multi-functional material that not only has high emission efficiency, but also possesses the effective hole trapping capability, which is useful for balancing hole/electron transport and controlling the emission zones when doped at appropriate locations of the device.     

The actor-critic algorithm as multi-time-scale stochastic approximation

The actor-critic algorithm of Barto and others for simulation-based optimization of Markov decision processes is cast as a two time scale stochastic approximation. Convergence analysis, approximation issues and an example are studied.     

Guest Editors' Introduction: On-Chip Interconnects for Multicores

This special issue of IEEE Micro brings readers the latest advances in the field of on-chip interconnects for multicores. The guest editors specifically selected articles to focus on novel on-chip networks realized on actual silicon--partly to showcase a few silicon prototypes of on-chip networks being used in multicore processors and SoCs; partly to bring to attention the implementation issues facing architects and designers. Along with six articles that gather insights from the designers of actual on-chip interconnects for multicores, the special issue includes two articles that delve into the design infrastructure support for on-chip networks and an article that summarizes the grand research challenges for realizing next-generation on-chip networks and multicores.     

Mobility enhancement by using silk fibroin in F16CuPc organic thin film transistors

High performance n-type F₁₆CuPc organic thin-film transistors (OTFTs) were fabricated on polyethylene terephthalate (PET) using silk fibroin as the gate dielectric. The average field-effect mobility (μ_FE) value in the saturation regime is 0.39 cm² V⁻¹ s⁻¹ approximately one order of magnitude higher than the reported values in the literature. A typical F₁₆CuPc OTFT exhibits an on/off current ratio of 9.3 × 10², a low threshold voltage of 0.65 V, and a subthreshold swing value of 730 mV/decade. The enhancement of μ_FE results from very good crystal quality of F₁₆CuPc on silk fibroin, supported by grazing incidence X-ray diffraction (GIXD) data.     

A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file

Describes a 256-word × 32-bit 4-read, 4-write ported register file for 6-GHz operation in 1.2-V 130-nm technology. The local bitline uses a pseudostatic technique for aggressive bitline active leakage reduction/tolerance to enable 16 bitcells/bitline, low-V_t usage, and 50% keeper downsizing. Gate-source underdrive of -V _cc on read-select transistors is established without additional supply/bias voltages or gate-oxide overstress. 8% faster read performance and 36% higher dc noise robustness is achieved compared to dual-V_t bitline scheme optimized for high performance. Device-level measurements in the 130-nm technology show 703× bitline active leakage reduction, enabling continued V_t scaling and robust bitline scalability beyond 130-nm generation. Sustained performance and robustness benefit of the pseudostatic technique against conventional dynamic bitline with keeper-upsizing is also presented     

A 4-GHz 130-nm address generation unit with 32-bit sparse-tree adder core

This paper describes a 32-bit address generation unit designed for 4-GHz operation in 1.2-V 130-nm technology. The AGU utilizes a 152-ps sparse-tree adder core to achieve 20% delay reduction, 80% lower interconnect complexity, and a low (1%) active energy leakage component. The dual-V/sub T/ semidynamic implementation of the adder core provides the performance of a dynamic CMOS design with an average energy profile similar to static CMOS, enabling 71% savings in average energy with a good sub-130-nm scaling trend.     

Tackling variability and reliability challenges

Variability and reliability will be the barriers to future technology scaling. Every discipline, from fabrication to software, needs to cooperate and make the VLSI system reliable in the presence of variability and the resulting inherent unreliability of components.