Corrosion behavior of Cu–Sn bronze alloys in simulated archeological soil media

The corrosion behavior of synthetic Cu–Sn bronze alloys with six different Sn contents was examined through an electrochemical test and a synthetic test in a simulated corrosive medium. The mechanism of corrosion and the morphology of the corroded surfaces were characterized through field emission scanning electron microscopy equipped with energy-dispersive spectroscopy. At the corrosion potential, the corrosion behavior appears to be determined by the charge transfer step and the diffusion process. It was found that the bronze-IV (Cu–26.8Sn) specimen exhibited the best corrosion resistance, as evidenced by a low corrosion current density and a high impedance. This improvement resulted from an increase in the content of the Cu–Sn solid solution in the alloy, which was conducive to forming a relatively more protective passive film on the surface of the bronze alloy. This finding would be valuable in the anticorrosion protection of archeological artefacts after their excavation.     

以辉锑矿为原料放电等离子烧结快速制备黝铜矿Cu_(12)Sb_4S_(13)及反应机理

采用辉锑矿为原料成功制备出Cu_(12)Sb_4S_(13)块体。研究以Sb_2S_3矿物为原料时烧结工艺对Cu_(12)Sb_4S_(13)合成的影响。在400 ～ 440℃温度区间内均可快速合成Cu_(12)Sb_4S_(13)块体且二次烧结能够进一步减小中间相CuSbS_2和Cu_3SbS_3。第二相Cu_3SbS_4和残留相CuS随着烧结时间的延长而降低。二次烧结前进行机械化球磨处理,干磨比湿磨更容易减小残留相。初次烧结块体的断面SEM和EDS能谱分析表明内部存在Cu或Cu_2S颗粒团聚现象。适当降低Cu或CuS摩尔量(化学计量比0.1 mol)能促进烧结块表面反应进行。烧结过程中,硫磺蒸汽压的导致烧结块表面成分和内部粉末的成分不同。     

基于射频技术的无刷同步电机励磁电流的检测

无刷同步电机的励磁系统对励磁电流的测量是制约该励磁方式发展的一大障碍。设计了一个射频系统可以用来解决同步电机的励磁电流的测量问题。该系统可以方便地检测到同步电机励磁机的整流二极管的工作状态并且可以动态地显示励磁电流，极大地方便了运行人员做出判断，而且结构简单、方便实用。     

变频器调速装置节能浅析

1概述 近十多年来,随着电力电子技术、微电子技术及现代控制理论的发展,变频调速技术已经广泛地用于交流电动机的速度控制,其最主要的特点是具有高效率的驱动性能及良好的控制特性.它是一种高新技术电力节能装置,它通过改变（降低）电源工作频率,来降低动力设备（电机）的转速,减少设备的输出功率,达到输出功率与工作负荷的最佳匹配,实现节能目的,有效地提高了经济效益和产品质量.几乎可以说,有电动机的地方就有变频器,在一切需要进行速度控制的场合,变频器以其操作方便、体积小、控制性能高而获得广泛应用.     

High-performance and power-efficient CMOS comparators

Several design techniques for high-performance and power-efficient CMOS comparators are proposed. First, the comparator is based on the priority-encoding (PE) algorithm, and the dynamic circuit technique developed specifically for the priority encoder can be applied. Second, the PE function and the subsequent logic functions are merged and efficiently realized in the multiple output domino logic (MODL) to result in a shortened logic depth. The circuit in MODL CMOS is also compact and power efficient because few transistors are needed. Third, the multilevel look-ahead technique is used to shorten the path of priority-token propagation. Finally, the circuit is realized with a latch-based two-stage pipelined structure, and the comparison function is partitioned into two parts, with each part executed in each half of the clock cycle in a delay-balanced manner. Post-layout simulation results show that a 64-b comparator designed with the proposed techniques in a 3-V 0.6-/spl mu/m CMOS technology is 16% faster, 50% smaller, and 79% more power efficient as compared with the all-n-transistor comparator, which is the fastest among the conventional comparators. Measurement results of the test chip conform with simulation results and prove the feasibility of the proposed techniques.     

Popular biorthogonal wavelet filters via a lifting scheme and its application in image compression

A technique using a lifting scheme is presented for constructing compactly supported wavelets whose coefficients are composed of free variables locating in an interval. An efficient approach-based wavelet for image compression is developed by selecting the coefficients of the 9-7 wavelet filter and associated lifting scheme. Furthermore, the rationalised coefficients wavelet filter that can be implemented with simple integer arithmetic is achieved and its characteristic is close to the well known original irrational coefficients 9-7 wavelet filters developed by A. Cohen et al. (Commun. Pure Appl. Maths., vol.45, no.1, p.485-560, 1992). To reduce the computational cost of image coding applications further, an acceleration technique is proposed for the lifting steps. Software and hardware simulations show that the new method has very low complexity, and simultaneously preserves the high quality of the compressed image.     

A 1.5-V 45-mW direct-conversion WCDMA receiver IC in 0.13-/spl mu/m CMOS

A 2-GHz direct-conversion receiver for wide-band code division multiple access (WCDMA) is presented. It includes two low-noise amplifiers (LNAs), an I/Q demodulator, and two sixth-order baseband channel select filters with programmable gain. Quadrature local oscillator (LO) signals are generated on chip in a frequency divider flip-flop. An external interstage filter between the LNAs rejects transmitter leakage to relax demodulator linearity requirements. A low-voltage demodulator topology improves linearity as well as demodulator output pole accuracy. The active-RC baseband filter uses a programmable servo loop for offset compensation and provides an adjacent channel rejection of 39 dB. Programmable gain over 71-dB range in 1-dB steps is merged with the filter to maximize dynamic range. An automatic on-chip frequency calibration scheme provides better than 1.5% corner frequency accuracy. The receiver is integrated in a 0.13-/spl mu/m CMOS process with metal-insulator-metal (MIM) capacitors. Measured receiver performance includes a 6.5-dB noise figure, IIP2 of +27 dBm, and IIP3 of -8.6 dBm. Power consumption is 45 mW.     

地震多次波压制方法技术应用研究

辽河盆地西部凹陷地质条件复杂，地震波场中多次波较发育，受其影响，主要目的层反射波干涉现象较严重，有效波难以识别，总体信噪比不高，给构造及岩性解释造成困难。对三维地震资料的处理研究表明，采用预测反褶积、F—K域多次波衰减技术及近道内切法等相结合的方法压制多次波是一种有效的途径。从资料处理效果看，剖面质量明显得到改善，证明该组合去噪技术是切实可行的。