CaPPS: cache partitioning with partial sharing for multi-core embedded systems

As the number of cores in chip multi-processor systems increases, the contention over shared last-level cache (LLC) resources increases, thus making LLC optimization critical, especially for embedded systems with strict area/energy/power constraints. We propose cache partitioning with partial sharing (CaPPS), which reduces LLC contention using cache partitioning and improves utilization with sharing configuration. Sharing configuration enables the partitions to be privately allocated to a single core, partially shared with a subset of cores, or fully shared with all cores based on the co-executing applications’ requirements. CaPPS imposes low hardware overhead and affords an extensive design space to increase optimization potential. To facilitate fast design space exploration, we develop an analytical model to quickly estimate the miss rates of all CaPPS configurations using the applications’ isolated LLC access traces to predict runtime LLC contention. Experimental results demonstrate that the analytical model estimates cache miss rates with an average error of only 0.73 % and with an average speedup of \(3505\times \) as compared to a cycle-accurate simulator. Due to CaPPS’s extensive design space, CaPPS can reduce the average LLC miss rate by as much as 25 % as compared to baseline configurations and as much as 14–17 % as compared to prior works.     

A Power Efficient Test Data Compression Method for SoC using Alternating Statistical Run-Length Coding

A power efficient System-on-a-Chip test data compression method using alternating statistical run-length coding is proposed. To effectively reduce test power dissipation, the test set is firstly preprocessed by 2D reordering scheme. To further improve the compression ratio, 4 m partitioning of the runs and a smart filling of the don’t care bits provide the nice results, and alternating statistical run-length coding scheme is developed to encode the preprocessed test set. In addition, a simple decoder is obtained which consumed a little area overhead. The benchmark circuits verify the proposed power efficient coding method well. Experimental results show it obtains a high compression ratio, low scan-in test power dissipation and little extra area overhead during System-on-a-Chip scan testing.     

A distributed range-free correction vector based localization refinement algorithm

Localization problem is an important and challenging topic in today’s wireless sensor networks. In this paper, a novel localization refinement algorithm for LAEP, which is a range-free localization algorithm by using expected hop progress, has been put forward. The proposed localization refinement algorithm, called as CVLR, is based on position correction vectors and can resolve the LAEP’s hop-distance ambiguity problem, which can lead to adjacent unknown nodes localized at the same or very close positions. CVLR can make full use of the relative position relationship of 1-hop neighboring nodes (called as CVLR1), or 1-hop and 2-hop neighboring nodes (called as CVLR2), to iteratively refine their localization positions. Furthermore, from localization accuracy and energy dissipation perspective, we optimize the communication process of CVLR2 and propose an energy-efficient improved CVLR. Simulation results show that the localization accuracy of CVLR1, CVLR2, and the improved CVLR are obviously higher than that of LAEP and DV-RND.     

A routing algorithm for reducing optical loss in photonic Networks-on-Chip

Driven by increase in automation, smart homes play an important role in today’s human life. This paper presents a new model for smart home technologies based on multi-device bidirectional visible light communication (VLC). For multiple devices and users, orthogonal code-based wavelength division (color beams) full-duplexed bidirectional VLC link is proposed. The color beams from RGB LEDs are utilized to transmit data and synchronize multi-device transmission. To enhance the performance of the proposed model, receiver diversity is also employed. Performance evaluation reveals that the proposed VLC-based model for smart homes is efficient with superior BER performance in a typical smart home environment except for the far corners. The maximum achievable data rate for each user up to four users is found to be 24 Mbps at both uplink and downlink transmissions.     

Resource efficiency improved approach for shared path protection in EONs

For improving the resource efficiency of dynamic shared path protection in elastic optical networks, a survivable RSA (SRSA)-based heuristic algorithm is proposed in the paper. In SRSA, an adaptive adjustment link cost function is devised to effectively select working and protection paths. The cost function sufficiently considers available spectrum resources and the length of light paths for both working and protection paths. In order to achieve high resource efficiency, a spectrum allocation strategy named minimal cost stable set is proposed to allocate spectrum for protection paths with respect to the resource efficiency in the link cost function. And the graph coloring algorithm is introduced to select the shared protection path with the highest resource efficiency for the request. Compared with the shared path protection and dynamic load balancing shared path protection, simulation results show that the proposed SRSA decreases bandwidth blocking probability and achieves high resource efficiency.     

Temperature compensated and gated CMOS ring oscillator for time-to-digital converter application

This paper presents a CMOS voltage controlled ring oscillator with temperature compensation for low power time-to-digital converters (TDCs). In order to maintain the oscillation frequency stable, a novel compensation circuit is proposed through adaptively sensing temperature variations. This design has been implemented in TSMC 0.35 μm CMOS standard process with an active area of under 0.039 mm². Experimental results show that the clock frequency is around 159.0 MHz only with a power consumption of 550 μA. As respective to the room temperature the maximum frequency variation is between ?3.46 and +3.08 % under temperature range of ?40 to 85 °C. The bit error time induced by clock jitter is limited within 4.8 % in the whole clock period, and the differential nonlinearity of the TDC is less than 0.408 LSB.     

An area-and-power-efficient 8.4-bit ENOB 30 MS/s SAR ADC in 65 nm CMOS

Area and power consumption are two main concerns for the electronics towards the digitalization of in-probe 3D ultrasound imaging systems. This work presents a 10-bit 30 MS/s successive approximation register analog-to-digital converter, which achieves good area efficiency as well as power efficiency, by using a symmetrical MSB-capacitor-split capacitor array with customized small-value finger capacitors. Moreover, simplified dynamic digital logic and a dynamic comparator have been designed. Fabricated in a 65 nm CMOS technology, the core circuit only occupies 0.016 mm². The ADC achieves a signal-to-noise ratio of 52.2 dB, and consumes 61.3 μW at 30 MS/s from a 1 V supply voltage, resulting in a figure of merit (FoM) of 6.2 fJ/conversion-step. The FoM defined by including the area is 0.1 mm² fJ/conversion-step.     

Switching scheme with 98.4% switching energy reduction and high accuracy for SAR ADCs

An energy-efficient digital-to-analogue converter (DAC) switching scheme with high-accuracy is proposed for successive approximation register (SAR) analogue-to-digital converters (ADCs). By utilizing a complementary switching method, the proposed switching scheme achieves a 98.4% switching energy reduction and a 75% area reduction compared to the conventional SAR ADC. Moreover, the accuracy of the SAR ADC is independent on the accuracy of the third reference voltage (V_cm) except the least significant bit, and the common-mode voltage of the DAC outputs keeps approximately unchanged during a conversion cycle, making the design of the SAR ADC more relaxed.     

Bio-cellular processes modeling on silicon substrate: receptor–ligand binding and Michaelis Menten reaction

Reducing transmit power is the most straightforward way towards more energy-efficient communications, but it results in lower SNRs at the receiver which can add a performance and/or complexity cost. At low SNRs, synchronization and channel estimation errors erode much of the gains achieved through powerful turbo and LDPC codes. Further expanding the turbo concept through an iterative receiver—which brings synchronization and equalization modules inside the loop—can help, but this solution is prohibitively complex and it is not clear what can and what cannot be a part of the iterative structure. This paper fills two important gaps in this field: (1) as compared to previous research which either focuses on a subset of the problem assuming perfect remaining parameters or is computationally too complex, we propose a proper partitioning of algorithm blocks in the iterative receiver for manageable delay and complexity, and (2) to the best of our knowledge, this is the first physical demonstration of an iterative receiver based on experimental radio hardware. We have found that for such a receiver to work, (1) iterative timing synchronization is impractical, iterative carrier synchronization can be avoided by using our proposed approach, while iterative channel estimation is essential, and (2) the SNR gains claimed in previous publications are validated in indoor channels. Finally, we propose a heuristic algorithm for simplifying the carrier phase synchronization in an iterative receiver such that computations of the log likelihood ratios of the parity bits can be avoided to strike a tradeoff between complexity and performance.