Design of 3.1–10.6 GHz ultra-wideband CMOS low noise amplifier with current reuse technique

A new low complexity ultra-wideband 3.1–10.6 GHz low noise amplifier (LNA), designed in a chartered 0.18 μm RFCMOS technology, is presented in this paper. The ultra-wideband LNA only consists of two simple amplifiers with an inter-stage inductor connected. The first stage utilizing a resistive current reuse and dual inductive degeneration techniques is used to attain a wideband input matching and low noise figure. A common source amplifier with inductive peaking technique as the second stage achieves high flat gain and wide the −3 dB bandwidth of the overall amplifier simultaneously. The implemented ultra-wideband LNA presents a maximum power gain of 15.6 dB, a high reverse isolation of −45 dB and a good input/output return losses are better than −10 dB in the frequency range of 3.1–10.6 GHz. An excellent noise figure (NF) of 2.8–4.7 dB was obtained in the required band with a power dissipation of 14.1 mW under a supply voltage of 1.5 V. An input-referred third-order intercept point (IIP3) is −7.1 dBm at 6 GHz. The chip area including testing pads is only 0.8 mm × 0.9 mm.     

Modern development methods and tools for embedded reconfigurable systems: A survey

Heterogeneous reconfigurable systems provide drastically higher performance and lower power consumption than traditional CPU-centric systems. Moreover, they do it at much lower costs and shorter times to market than non-reconfigurable hardware solutions. They also provide the flexibility that is often required for the engineering of modern robust and adaptive systems. Due to their heterogeneity, flexibility and potential for highly optimized application-specific instantiation, reconfigurable systems are adequate for a very broad class of applications across different industry sectors. What prevents the reconfigurable system paradigm from a broad proliferation is the lack of adequate development methodologies and electronics design tools for this kind of systems. The ideal would be a seamless compilation of a high-level computation process specification into an optimized mixture of machine code executed on traditional CPU-centric processors and on the application-specific decentralized parallel data-flow-dominated reconfigurable processors and hardware accelerators. Although much research and development in this direction was recently performed, the adequate methodologies and tools necessary to implement this compilation process as an effective and efficient hardware/software co-synthesis flow are unfortunately not yet in place. This paper focuses on the recent developments and development trends in the design methods and synthesis tools for reconfigurable systems. Reconfigurable system synthesis performs two basic tasks: system structure construction and application process mapping on the structure. It is thus more complex than standard (multi-)processor-based system synthesis for software-programmable systems that only involves application mapping. The system structure construction may involve the macro-architecture synthesis, the micro-architecture synthesis, and the actual hardware synthesis. Also, the application process mapping can be more complicated and dynamic in reconfigurable systems. This paper reviews the recent methods and tools for the macro- and micro-architecture synthesis, and for the application mapping of reconfigurable systems. It puts much attention to the relevant and currently hot topic of (re-)configurable application-specific instruction set processors (ASIP) synthesis, and specifically, ASIP instruction set extension. It also discusses the methods and tools for reconfigurable systems involving CPU-centric processors collaborating with reconfigurable hardware sub-systems, for which the main problem is to decide which computation processes should be implemented in software and which in hardware, but the hardware/software partitioning has to account for the hardware sharing by different computation processes and for the reconfiguration processes. The reconfigurable system area is a very promising, but quite a new field, with many open research and development topics. The paper reviews some of the future trends in the reconfigurable system development methods and tools. Finally, the discussion of the paper is summarized and concluded.     

Statistical analysis of large on-chip power grid networks by variational reduction scheme

One of the most critical challenges in today's CMOS VLSI design is the lack of predictability in chip performance at design stage. One of the process variabilities comes from the voltage drop variations in on-chip power distribution networks. In this paper, we present a novel analysis approach for computing voltage drops of large power grid networks under process variations. The new algorithm is very efficient and scalable for huge networks with a large number of variational variables. This approach, called variational extended truncated balanced realization (varETBR), is based on model order reduction techniques to reduce the circuit matrices before the variational simulation. It performs the parameterized reduction on the original system using variation-bearing subspaces. After the reduction, Monte Carlo based statistical simulation is performed on the reduced system and the statistical responses of the original system are obtained thereafter. varETBR calculates variational response Grammians by Monte Carlo based numerical integration considering both system and input source variations in generating the projection subspace. varETBR is very scalable for the number of variables and flexible for different variational distributions and ranges as demonstrated in experimental results. Experimental results, on a number of IBM benchmark circuits up to 1.6 million nodes, show that the varETBR can be 1900X faster than the Monte Carlo method and is much more scalable than one of the recently proposed approaches.     

Technological development of Brazilian telecommunications in past decades

Brazilian telecommunications sector has undergone important modifications in the last 40 years. From a badly structured system of municipal level operators in 1960, with barely one million fixed lines to a large, nation-wide system with about 50 million fixed plus another 75 million mobile lines in 2005. This work paper reviews the institutional framework of telecommunications industrial and technological policy in Brazil in the last four decades, its results and present situation. Infrastructure and services modernisation and expansion process that happened in early 1970s were carried out at the expense of massive import of products and technology. A government strategy was, then, devised to stimulate local industrial and technological development in telecommunications, under the general guidelines of import substitution policy. Essential to this strategy was the creation of an innovation system around TELEBRÁS Research and Development Centre. This technological development model was successful while a protectionist economic policy existed. When economic and political circumstances could not anymore sustain an import substitution approach, in the 1990-decade, the model fell apart and has not been replaced by any other sectorial policy. A critical assessment is carried out, analysing the adopted actions in face of the digital technology maturing process that occurred in meantime.     

Cad for analysis and synthesis of MM-wave transmission lines

This work presents a software for analysis and synthesis of four types of planar lines used on the millimeter wave band: Suspended Microstrip Line, Inverted Microstrip Line, Suspended Stripline and Broadside Coupled Stripline. Conceived for IBM/PG or compatible microcomputers, the program, (MMWL), can study each configuration at a time or all of them at once, and it does not matter if it is synthesis or analysis for each line at the same time. The results are presented in Tables shown in the same screen. The program also provides curves of characteristic impedances against conducting strip width for each one of studied structures. Therefore, it allows choosing the best combination for circuit realization, becoming a helpful tool for projects and with acceptable results.

     

What do we want specifically from the cell phone? An age related study

This study investigated the evolution of specific cell phone feature preferences among high school, undergraduate and graduate college students in Finland. Following the relevant literature review, the paper analyzed the responses of 118 high school, 268 undergraduate and 84 graduate students from educational institutions located in the metropolitan area of Tampere, Finland. The results indicate that the students in Finland appreciate the specific feature “clock”, “phone”, “high battery life”, “alarm”, and “calendar” as very important, and the specific features “TV connectivity”, “joystick”, “live TV”, “Twitter”, and “small screen size” as unimportant features. There were also significant differences in the specific feature preferences between the students between high school, undergraduate and graduate students. In addition there were differences in the way the respondents conceptualize the specific feature preferences of the cell phone. The paper concludes with a discussion regarding the academic and managerial implications.     

QoS for wireless sensor networks: Enabling service differentiation at the MAC sub-layer using CoSenS

Providing service differentiation in wireless sensor networks while proposing simple and highly scalable solution is a challenging problem. We retain the use of CSMA/CA as access protocol because of its simplicity, versatility and good scalability properties. We developed CoSenS, a Collect then Send burst Scheme, on top of it to address its weaknesses while facilitating the implementation of scheduling policies. In this article, we propose a simple and scalable service differentiation solution; we implement fixed priority and earliest deadline first on top of CoSenS. The simulation analysis shows that our solution self-adapts to the traffic variation and greatly enhances end-to-end delay, reliability and deadline meet ratio for urgent traffic while not degrading best effort traffic compared to IEEE 802.15.4 original protocol and IEEE 802.15.4 implementing these scheduling policies. Additionally, CoSenS is implemented and tested on motes. The real experimentation results validated our simulation analysis.     

Estimation of breast tumor thermal properties using infrared images

The major goal of this paper is to help detect breast cancer early based on infrared images. Some procedures, protocols and numerical simulations were developed or performed. Two different issues are presented. The first is the development of a standardized protocol for the acquisition of breast thermal images including the design, construction and installation of mechanical apparatus. The second part is related to the greatest difficulty for the numerical computation of breast temperature profiles that is caused by the uncertainty of the real values of the thermophysical parameters of some tissues. Then, a methodology for estimating thermal properties based on these infrared images is presented. The commercial software FLUENT^TM was used for the numerical simulation. A Sequential Quadratic Programming (SQP) method was used to solve the inverse problem and to estimate the thermal conductivity and blood perfusion of breast tissues. The results showed that it is possible to estimate the thermophysical properties using the thermography. The next stage will be to use the geometry of a real breast for the numerical simulation in conjunction with a linear mapping of the temperatures measured over the breast volume.     

Implicit FSM decomposition applied to low-power design

Clock-gating techniques are very effective in the reduction of the switching activity in sequential logic circuits. In this paper, we describe a clock-gating technique based on finite-state machine (FSM) decomposition. The approach is based on the computation of two sub-FSMs that together have the same functionality as the original FSM. For all the transitions within one sub-FSM, the clock for the other sub-FSM is disabled. To minimize the average switching activity, we search for a small cluster of states with high stationary state probability and use it to create the small sub-FSM. Explicit manipulation of the state transition graph requires time and space exponential on the number of registers in the circuit, thereby restricting the applicability of explicit methods to relatively small circuits. The approach we propose is based on a method that implicitly performs the FSM decomposition. Using this technique, the FSM decomposition is performed by direct manipulation of the circuit. We provide a set of experiments that show that power consumption can be substantially reduced, in some cases by more than 70%.