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991.
Translated from Khimicheskoe i Neftyanoe Mashinostroenie, No. 7, pp. 1–2, July, 1992.  相似文献   
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The cost of electricity and operating reliability in heavy industry can be key in determining which processes and plants survive in today's competitive market. This paper provides an insight into the planning and implementation of several significant cost saving and reliability improvements at a turn-of-the-century steel mill in Ohio. A clear understanding of what to look for and how to proceed with such projects should provide motivation for others considering similar improvements  相似文献   
997.
This paper develops a method for simultaneously designing the power stage and controller for a switching power supply. The method utilizes a numerical optimization procedure, which facilitates computer-aided design. It is found that better performance can be achieved than with a traditional two-step design process, where the power stage and controller are designed sequentially. Optimization and simulation results for a buck power converter are presented to illustrate the design process and benefits  相似文献   
998.
Soluble mitochondrial F1 and F1 in complex with the natural ATPase inhibitor protein (F1-IP) catalyze the spontaneous synthesis of [gamma-32P]ATP from medium [32P]phosphate and enzyme-bound ADP when incubated in media with dimethylsulfoxide (Me2SO); under these conditions, the synthesized [gamma-32P]ATP is not released into the media, it remains tightly bound to the enzymes [Gómez-Puyou, A., Tuena de Gómez-Puyou, M. & de Meis, L. (1986) Eur. J. Biochem. 159, 133-140]. Some of the characteristics of the synthesized [gamma-32P]ATP were studied in F1 and F1-IP (ATPase activities of 70 and 1-3 micromol x min(-1) x mg(-1), respectively). In Me2SO media, gamma-phosphate of synthesized ATP in F1 or F1-IP exchanges with medium phosphate. From the rates of the exchange reaction, the half-times for hydrolysis of the synthesized ATP in F1 and F1-IP were calculated: 45 min and 58 min for F1 and F1-IP, respectively. The course that synthesized [gamma-32P]ATP follows after dilution of the Me2SO synthetic mixture with aqueous buffer was determined. After dilution, the half-life of synthesized ATP in F1 was less than 1 min. In F1-IP, ATP was also hydrolyzed, but at significantly lower rates. In F1-IP, dilution also produced release of the synthesized [gamma-32P]ATP. This was assayed by the accessibility of [gamma-32P]ATP to hexokinase. About 25% of [gamma-32P]ATP synthesized in F1-IP, but not in F1, was released into the media after dilution with aqueous buffer that contained 20 mM phosphate. Release of tightly bound ATP required the binding energy of phosphate and solvation of F1-IP, however, the particular kinetics of F1-IP were also central for medium ATP synthesis in the absence of electrochemical H+ gradients.  相似文献   
999.
OBJECTIVE: To evaluate the intravitreal tolerance of a new perfluorocarbon vitreous replacement, Multifluor APF-144 (perfluorotetramethylcyclohexane). DESIGN: Ten New Zealand albino rabbits (one eye from each) underwent vitrectomy. The vitreous was replaced in five eyes with Multifluor APF-144 and in five eyes with saline (control group). OUTCOME MEASURES: Appearance on indirect ophthalmoscopy, electroretinography recordings before and 2, 4 and 8 weeks after vitrectomy, findings on electron and light microscopy at 8 weeks. RESULTS: Endophthalmitis did not develop in any of the eyes. There was no significant change in electroretinography values for the experimental eyes after vitrectomy. No evidence of retinal toxicity was found on light or electron microscopic examination. CONCLUSIONS: Multifluor APF-144 shows promise as a short-term postoperative retinal tamponading agent.  相似文献   
1000.
The trade-off between threshold voltage (Vth) and the minimum gate length (Lmin) is discussed for optimizing the performance of buried channel PMOS transistors for low voltage/low power high-speed digital CMOS circuits. In a low supply voltage CMOS technology it is desirable to scale Vth and Lmin for improved circuit performance. However, these two parameters cannot be scaled independently due to the channel punch-through effect. Statistical process/device modeling, split lot experiments, circuit simulations, and measurements are performed to optimize the PMOS transistor current drive and CMOS circuit speed. We show that trading PMOS transistor Vth for a smaller Lmin results in faster circuits for low supply voltage (3.3 to 1.8 V) n+-polysilicon gate CMOS technology, Circuit simulation and measurements are performed in this study. Approximate empirical expressions are given for the optimum buried channel PMOS transistor V th for minimizing CMOS circuit speed for cases involving: (1) constant capacitive load and (2) load capacitance proportional to MOS gate capacitance. The results of the numerical exercise are applied to the centering of device parameters of a 0.5 μm 3.3 V CMOS technology that (a) matches the speed of our 0.5 μm 5 V CMOS technology, and (b) achieves good performance down to 1.8 V power supply. For this process the optimum PMOS transistor Vth (absolute value) is approximately 0.85-0.90 V  相似文献   
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