用于130nm/90nm新工艺开发的铜CMP阻挡层磨料系统(英文)

通过与实验室的CMP和集成工程师合作,采用测试系统观察两种或两种以上混合配方磨料的选择比。实验数据表明,通过改变单个化学试剂组分的浓度改变磨料的选择比效果突出,磨料配方师可以简便地修改磨料配方。这种方法的优点是,如果改变集成方法或特殊膜层,可以很快地重新优化磨料。如SiN膜取代TEOW淀积氧化物膜,对新系统可以容易地重新优化磨料。介绍了几种磨料组分浓度的去除速率和选择比。     

Self‐Healing Reduced Graphene Oxide Films by Supersonic Kinetic Spraying

The industrial scale application of graphene and other functional materials in the field of electronics has been limited by inherent defects, and the lack of simple deposition methods. A simple spray deposition method is developed that uses a supersonic air jet for a commercially available reduced graphene oxide (r‐GO) suspension. The r‐GO flakes are used as received, which are pre‐annealed and pre‐hydrazine‐treated, and do not undergo any post‐treatment. A part of the considerable kinetic energy of the r‐GO flakes entrained by the supersonic jet is used in stretching the flakes upon impact with the substrate. The resulting “frozen elastic strains” heal the defects (topological defects, namely Stone‐Wales defect and C₂ vacancies) in the r‐GO flakes, which is reflected in the reduced ratio of the intensities of the D and G bands in the deposited film. The defects can also be regenerated by annealing.     

一个应用于数字音频的高性能、低功耗ΣΔ模数转换器

本文介绍了一个应用于18位高端音频的ΣΔ模数转换器(ADC)。它包括一个2-1级联结构的ΣΔ调制器和一个数字抽取滤波器。在系统设计、电路实现和版图设计的过程中采取了许多优化措施,包括：选择了一个能够实现高过载水平的调制器结构并对其系数进行优化,实现了一个高能效的A/AB 类跨导放大器和一个面积和功耗优化的多级抽取滤波器。模数转换器在中芯国际0.18μm 混合信号CMOS 工艺中流片。测试结果表明在22.05 KHz带宽内,信噪失真比和动态范围分别达到91dB和94dB,而芯片面积为2.1 mm2,其中模拟部分仅消耗2.1mA静态电流。     

Compact Harmonic Filter Design and Fabrication Using IPD Technology

An integrated passive device (IPD) technology has been developed to meet the ever increasing needs of size and cost reduction in radio front-end transceiver module applications. Electromagnetic (EM) simulation was used extensively in the design of the process technology and the optimization of inductor and harmonic filter designs and layouts. Parameters such as inductor shape, inner diameter, metal thickness, metal width, and substrate thickness have been optimized to provide inductors with high quality factors. The technology includes 1) a thick plated gold metal process to reduce resistive loss; 2) MIM capacitors using PECVD SiN dielectric layer; 3) airbridges for inductor underpass and capacitor pick-up; and 4) a 10 mil finished GaAs substrate to improve inductor quality factor. Both lumped element circuit simulations and electromagnetic (EM) simulations have been used in the harmonic filter circuit designs for high accuracy and fast design cycle time. This paper will present the EM simulation calibration and demonstrate the importance of using EM simulation in the filter design in order to achieve first-time success in wafer fabrication. The fabricated IPD devices have insertion loss of 0.5 dB and harmonic rejections of 30dB with die size of 1.42 mm for high band (1710 MHz-1910 MHz) and 1.89 mm for low band (824-915 MHz) harmonic filters.     

High Performance CMOS Analog Arithmetic Circuits

Unique designs for CMOS analog arithmetic circuits are presented which perform addition (V₁ + V₂), subtraction (V₂ – V₁), add/invert –(V₁ + V₂), and multiply (V₁ × V₂). The circuit operation is based on the inherent square law of MOS transistor drain current when operating in the saturation region. Key features include: good linearity and accuracy, single ended voltage inputs and output, wide input and output range and no input bias voltages. The circuits can be directly coupled (no buffer) and serve as basic building blocks for analog signal processing implementations such as analog filters and adaptive equalizers. All circuits were implemented in 1.2 m CMOS technology.     

Analysis of external latch-up protection test structure design using numerical simulation

With each new CMOS technology the latch-up sensitivity and effects of prevention strategies change. Products built in these technologies must adhere to stringent guidelines for latch-up ‘Hardness’, and for this reason characterisation of new technologies is needed through the use of test structures. This paper shows a numerical simulation approach which can determine the relative effectiveness of guard-rings in ESD protection device test structures. In this work, time taken to characterise latch-up protection test structures and to chose a protection strategy is greatly reduced by using numerical simulations to design the test structures. The results presented are for variations to the guard-rings for two technologies. Included in these are the typical simulation times and resources required. The technique outlined has the joint advantages of providing accurately representative simulations of the technology and test structure layout in a practical time frame.     

1985年以来低温制冷机的研制和应用(节译)

大约从1985年开始,低温制冷机取得许多重大的新进展,使制冷机在效率、寿命、紧凑性和最低极限温度方面均有较大的突破。如电力能源的高温超导体,卫星用红外探测器、核磁共振成像(MRI)系统的超导磁体冷却,低温外科手术,以及医学、工业和空间应用的小型气体液化。本文揭示各种类型低温制冷机的新的进展,如何提高制冷机的性能来满足一些新的应用。     

聚合物波导电光调制器

尽管直接调制激光二级管控制光波是一种简单是一种简单且重要的调制方式，但光波导结构的调制器将使器件性能得到惊人的改善，本文简略介绍了聚合物波导电光调制器，并给出了制备该器件的聚合物材料及制备过程。     

A 4-91-GHz traveling-wave amplifier in a standard 0.12-/spl mu/m SOI CMOS microprocessor technology

This paper presents five-stage and seven-stage traveling-wave amplifiers (TWA) in a 0.12-/spl mu/m SOI CMOS technology. The five-stage TWA has a 4-91-GHz bandpass frequency with a gain of 5 dB. The seven-stage TWA has a 5-86-GHz bandpass frequency with a gain of 9 dB. The seven-stage TWA has a measured 18-GHz noise figure, output 1-dB compression point, and output third-order intercept point of 5.5 dB, 10 dBm, and 15.5 dBm, respectively. The power consumption is 90 and 130 mW for the five-stage and seven-stage TWA, respectively, at a voltage power supply of 2.6 V. The chips occupy an area of less than 0.82 and 1 mm for the five-stage and seven-stage TWA, respectively.     

A novel DSP‐based PFC‐DPLL with fuzzy controlled acquisition aid to improve acquisition performance and noise immunity

This paper proposes a new digital signal processing (DSP)‐based phase frequency controlled digital phase locked loop. Here, a very simplistic form of fuzzy logic controller with the help of carrier phase and frequency error as input data is used to provide an acquisition aid. A frequency discriminator is employed to generate frequency error, and phase detector output is taken for phase error. This addition of an acquisition aid helps the loop to achieve the minimum acquisition time and maximum noise rejection simultaneously. An additional phase control in the digitally controlled oscillator makes the loop perform even better towards this goal. The implementation of the proposed loop is carried out on a reconfigurable logic platform using System Generator^®;, a tool from Xilinx^®; used to design real‐time DSP application. A significant improvement of time domain characteristics are observed as well as the performance in presence of additive white Gaussian noise is demonstrated in terms of the reduction in steady‐state phase jitter and enhancement in output signal to noise ratio in the proposed loop. Copyright © 2014 John Wiley & Sons, Ltd.