Separated two-phase flow regime parameter measurement by a high speed ultrasonic pulse-echo system

In this work, a high speed ultrasonic multitransducer pulse-echo system using a four transducer method was used for the dynamic characterization of gas-liquid two-phase separated flow regimes. The ultrasonic system consists of an ultrasonic pulse signal generator, multiplexer, 10 MHz (0.64 cm) ultrasonic transducers, and a data acquisition system. Four transducers are mounted on a horizontal 2.1 cm inner diameter circular pipe. The system uses a pulse-echo method sampled every 0.5 ms for a 1 s duration. A peak detection algorithm (the C-scan mode) is developed to extract the location of the gas-liquid interface after signal processing. Using the measured instantaneous location of the gas/liquid interface, two-phase flow interfacial parameters in separated flow regimes are determined such as liquid level and void fraction for stratified wavy and annular flow. The shape of the gas-liquid interface and, hence, the instantaneous and cross-sectional averaged void fraction is also determined. The results show that the high speed ultrasonic pulse-echo system provides accurate results for the determination of the liquid level within +/-1.5%, and the time averaged liquid level measurements performed in the present work agree within +/-10% with the theoretical models. The results also show that the time averaged void fraction measurements for a stratified smooth flow, stratified wavy flow, and annular flow qualitatively agree with the theoretical predictions.     

Electrical Stress Degradation of Small-Grain Polysilicon Thin-Film Transistors

This paper is focused on the stability of n-channel laser-crystallized polysilicon thin-film transistors (TFTs) submitted to a hydrogenation process during the fabrication and with small grains dimension. With the aid of numerical simulations, we investigate the effects of static stress using two types of procedures: the on stress and the hot carrier stress. Results show that the variations of trap state density into the whole polysilicon layer and not only near the drain junction are responsible for the degradation of TFTs performances in both the two types of stress and that the interface trap states play a negligible role compared to the bulk trap states