A Statistical Metadata Model for Simultaneous Manipulation of both Data and Metadata

There is a growing demand for more cost-efficient production processes in Statistical Institutes. One way to address this need is to equip Statistical Information Systems (SIS) with the ability to automatically produce statistical data and metadata of high quality and deliver them to the user via the Internet. Current approaches, although provide for the storage of appropriate metadata, do not use process metadata for guiding the production process. In this paper we present an approach on creating SISs that permits metadata-guided statistical processing based on an object-based, statistical metadata model. The model is not domain specific and can accommodate both microdata and macrodata. We have equipped the model with a set of transformations that can be used to automatically manipulate data and metadata. We show the applicability of transformations with some examples using actual statistical data for R&D expenditures. Finally, we demonstrate how the presented framework can be exploited for the construction of a web site that offers ad hoc query capabilities to the users of statistical data.     

Partitioning Methodology for Heterogeneous Reconfigurable Functional Units

A partitioning methodology between the reconfigurable hardware blocks of different granularity, which are embedded in a generic heterogeneous architecture, is presented. The fine-grain reconfigurable logic is realized by an FPGA unit, while the coarse-grain reconfigurable hardware by a 2-Dimensional Array of Processing Elements. Critical parts, called kernels, are mapped on the coarse-grain reconfigurable logic for improving performance. The partitioning method is mainly composed by three steps: the analysis of the input code, the mapping onto the Coarse-Grain Reconfigurable Array and the mapping onto the FPGA. The partitioning flow is implemented by a prototype software framework. Analytical partitioning experiments, using five real-world applications, show that the execution time speedup relative to an all-FPGA solution ranges from 1.4 to 5.0.     

Design space exploration of an optimized compiler approach for a generic reconfigurable array architecture

Several mesh-like coarse-grained reconfigurable architectures have been devised in the last few years accompanied with their corresponding mapping flows. One of the major bottlenecks in mapping algorithms on these architectures is the limited memory access bandwidth. Only a few mapping methodologies encountered the problem of the limited bandwidth while none has explored how the performance improvements are affected, from the architectural characteristics. We study in this paper the impact that the architectural parameters have on performance speedups achieved when the PEs’ local RAMs are used for storing the variables with data reuse opportunities. The data reuse values are transferred in the internal interconnection network instead of being fetched, from external memories, in order to reduce the data transfer burden on the bus network. A novel mapping algorithm is also proposed that uses a list scheduling technique. The experimental results quantified the trade-offs that exist between the performance improvements and the memory access latency, the interconnection network and the processing element’s local RAM size. For this reason, our mapping methodology targets on a flexible architecture template, which permits such an exploration. More specifically, the experiments showed that the improvements increase with the memory access latency, while a richer interconnection topology can improve the operation parallelism by a factor of 1.4 on average. Finally, for the considered set of benchmarks, the operation parallelism has been improved from 8.6% to 85.1% from the application of our methodology, and by having each PE’s Local RAM a size of 8 words.

Unsupervised 2D gel electrophoresis image segmentation based on active contours

This work introduces a novel active contour-based scheme for unsupervised segmentation of protein spots in two-dimensional gel electrophoresis (2D-GE) images. The proposed segmentation scheme is the first to exploit the attractive properties of the active contour formulation in order to cope with crucial issues in 2D-GE image analysis, including the presence of noise, streaks, multiplets and faint spots. In addition, it is unsupervised, providing an alternate to the laborious, error-prone process of manual editing, which is required in state-of-the-art 2D-GE image analysis software packages. It is based on the formation of a spot-targeted level-set surface, as well as of morphologically-derived active contour energy terms, used to guide active contour initialization and evolution, respectively. The experimental results on real and synthetic 2D-GE images demonstrate that the proposed scheme results in more plausible spot boundaries and outperforms all commercial software packages in terms of segmentation quality.     

Low-temperature thermal drying of Saccharomyces cerevisiae starter culture for food production

The production of low-temperature thermally-dried cells of Saccharomyces cerevisiae at 32 °C is examined in the present investigation. Cells are obtained in a thin layer after heating for 4 h in an incubator. This thermally-dried starter culture showed acceptable fermentation efficiency, proved by repeated batch fermentations of glucose. The starter culture, when compared with freeze-dried cells, showed better fermentation ability. Storage of thermally-dried S. cerevisiae for one month showed resistance to loss of fermentation efficiency. The chemical composition of volatiles produced during fermentation were similar to those obtained with freeze-dried and wet starter culture fermentations. The thermally-dried cells effectively ferment at low temperatures.     

Weight-modeling of B2C system quality

The efficiency and cost effectiveness of internet technologies have already transformed the web into a global environment for business. However, designing, developing and supporting e-commerce systems having quality in mind is a challenging task. The quality of a Business to Consumer system may be assessed from two complementary, orthogonal, points of view: as a software system and as a service to end-users/customers. As a software system it must be assessed by professional software engineers, the evaluators. They are best in assessing top down the system. As a service it must be assessed by customer's perspective, the end-user. They provide a bottom up evaluation approach of the system. In this work, these points of view are combined in a weighted model which uses the external quality characteristics and sub-characteristics of ISO9126 as a baseline for further decomposition into technical and user-oriented features. The model can be used forward and backwards: forward for evaluating in detail the qualitative strengths and weaknesses of an existing B2C system; backwards for balancing quality improvement with development criteria.     

Modelling nitrogen in the Yeşilirmak River catchment in Northern Turkey: impacts of future climate and environmental change and implications for nutrient management

Recent research in catchments of rapidly developing countries such as Brazil and China suggests that many catchments of the developing world are already showing signs of nitrogen pollution reminiscent of past experiences in developed countries. This paper looks at both the individual and combined effects of future climate change and other likely environmental changes on in-stream nitrate concentrations in a catchment in Northern Turkey. A model chain comprised of simulated future temperature and precipitation from a Regional Circulation Model (RCM), a conceptual hydrological model (HBV) and a widely tested integrated catchment nitrogen model (INCA-N) is used to model future changes in nitrate concentrations. Two future periods (2021-2050 and 2069-2098) are compared to the 1961-1990 baseline period in order to assess the effectiveness of several possible interventions available to catchment authorities. The simulations show that in the urbanised part of the catchment, the effects of climate change and other environmental changes act in the same direction, leading to peak nitrate concentrations of 7.5 mg N/l for the 2069-2098 period, which corresponds to a doubling of the baseline values. Testing different available policy options reveals that the installation of wastewater treatment works (WWTWs) in all major settlements of the catchment could ensure nitrate levels are kept at near their baseline values for the 2021-2050 period. Nevertheless, a combination of measures including WWTWs, meadow creation, international agreements to reduce atmospheric N concentrations and controls on agricultural practises will be required for 2069-2098. The approach presented in this article could be employed in order to anticipate future pollution problems and to test appropriate solutions, some of which will necessitate international co-operation, in other catchments around the world.     

Performance Improvements from Partitioning Applications to FPGA Hardware in Embedded SoCs

A hardware/software partitioning methodology for improving performance in single-chip systems composed by processor and Field Programmable Gate Array reconfigurable logic is presented. Speedups are achieved by executing critical software parts on the reconfigurable logic. A hybrid System-on-Chip platform, which can model the majority of existing processor-FPGA systems, is considered by the methodology. The partitioning method uses an automated kernel identification process at the basic-block level for detecting critical kernels in applications. Three different instances of the generic platform and two sets of benchmarks are used in the experimentation. The analysis on five real-life applications showed that these applications spend an average of 69% of their instruction count in 11% on average of their code. The extensive experiments illustrate that for the systems composed by 32-bit processors the improvements of five applications ranges from 1.3 to 3.7 relative to an all software solution. For a platform composed by an 8-bit processor, the performance gains of eight DSP algorithms are considerably greater, as the average speedup equals 28.