Design Methodology for Offloading Software Executions to FPGA

Field programmable gate array (FPGA) is a flexible solution for offloading part of the computations from a processor. In particular, it can be used to accelerate an execution of a computationally heavy part of the software application, e.g., in DSP, where small kernels are repeated often. Since an application code for a processor is a software, a design methodology is needed to convert the code into a hardware implementation, applicable to the FPGA. In this paper, we propose a design method, which uses the Transport Triggered Architecture (TTA) processor template and the TTA-based Co-design Environment toolset to automate the design process. With software as a starting point, we generate a RTL implementation of an application-specific TTA processor together with the hardware/software interfaces required to offload computations from the system main processor. To exemplify how the integration of the customized TTA with a new platform could look like, we describe a process of developing required interfaces from a scratch. Finally, we present how to take advantage of the scalability of the TTA processor to target platform and application-specific requirements.     

Adaptive Modeling of Analog/RF Circuits for Efficient Fault Response Evaluation

In this paper, we propose a methodology for adaptive modeling of analog/RF circuits. This modeling technique is specifically geared towards evaluating the response of a faulty circuit in terms of its specifications and/or measurements. The goal of this modeling approach is to compute important test metrics, such as fail probability, fault coverage, and/or yield coverage of a given measurement under process variations. Once the models for the faulty and fault-free circuit are generated, we can simply use Monte-Carlo sampling (as opposed to Monte-Carlo simulations) to compute these statistical parameters with high accuracy. We use the error budget that is defined in terms of computing the statistical metrics and the position of the threshold(s) to decide how precisely we need to extract the necessary models. Experiments on LNA and Mixer confirm that the proposed techniques can reduce the number of necessary simulations by factor of 7 respectively, in the computation of the fail probability.     

Photoluminescence and Raman Spectroscopy of Polycrystalline ZnO Nanofibers Deposited by Electrospinning

The technique of electrospinning offers the advantage of growing nanowires in bulk quantities in comparison with traditional methods. We report optical studies of polycrystalline zinc oxide (ZnO) nanofibers (∼100 nm thick and 5 μm long) deposited by electrospinning. Photoluminescence from the nanofibers shows a near-ultraviolet (near-UV) peak corresponding to near-band-edge emission and a strong broad peak in the visible region from oxygen antisite and interstitial defects. Temperature-dependent photoluminescence spectroscopy reveals that different carrier recombination mechanisms are dominant at low temperature. Our Raman spectroscopy results demonstrate that characterization of the quasimodes of longitudinal optical (LO) and transverse optical (TO) phonons present in an ensemble of polycrystalline nanofibers tilted at various angles in addition to the dominant E ₂(high) mode provides a promising technique for assessing the quality of such randomly oriented nanowires.     

RAI: A High Throughput Routing Protocol for Multi-hop Multi-rate Ad hoc Networks

The advantages of using the multiple rates for wireless communications have been revealed in the recent years. To determine the appropriate rate and to make routing decision more precise, the communication nodes need the information from lower layer. Therefore, in this paper, a high throughput routing protocol using lower layer information for Multi-rate Ad-hoc Networks is proposed. We introduce a new routing metric named “Route Assessment Index” (RAI). The route with maximum RAI value is preferred to achieve the high throughput route, and to avoid the link bottleneck for reducing the packet drop rate. The chosen route also has a small number of hops. The routing protocol works in distributed manner, and correctness of the proposal is proven. The simulation results show that our new metric provides an accurate and efficient method for assessing and selecting the best route in Multi-rate Ad-hoc Networks.     

MRI-compatible intensity-modulated force sensor for cardiac catheterization procedures

This paper presents a novel, magnetic resonance imaging (MRI)-compatible, force sensor suitable for cardiac catheterization procedures. The miniature, fiber-optic sensor is integrated with the tip of a catheter to allow the detection of interaction forces with the cardiac walls. The optical fiber light intensity is modulated when a force acting at the catheter tip deforms an elastic element, which, in turn, varies the distance between a reflector and the optical fiber. The tip sensor has an external diameter of 9 Fr (3?mm) and can be used during cardiac catheterization procedures. The sensor is able to measure forces in the range of 0-0.85?N, with relatively small hysteresis. A nonlinear method for calibration is used and real-time MRI in vivo experiments are carried out, to prove the feasibility of this low-cost sensor, enabling the detection of catheter-tip contact forces under dynamic conditions.     

A Behavioral Model of MEMS Convective Accelerometers for the Evaluation of Design and Calibration Strategies at System Level

This paper presents a behavioral model that can be used to improve the manufacturability of systems based on MEMS convective sensors. This model permits to handle faults related to process scattering, taking into account not only the electrical and lateral geometrical parameters but also the influence of the cavity depth. Moreover correlations between conductive and convective phenomena are included. The model is validated with respect to FEM simulations and a very good agreement is obtained between the behavioral model and FEM results. The proposed model can then be used in system-level simulations, for instance to evaluate the impact of process scattering on the performances of the sensing part and/or to investigate different design and calibration strategies with respect to the system robustness.     

Computing the Detection Probability for Small Delay Defects of Nanometer ICs

Interconnect imperfections have become an important issue in modern nanometer technologies. Some of them cause Small Delay Defects (SDDs) which are difficult to detect. Those SDDs not detected during testing may pose a reliability problem. Furthermore, nanometer issues (e.g. process variations, spatial correlations) represent important challenges for traditional delay test methods. In this paper, a methodology to compute the Detection Probability (DP) of resistive open and bridge defects using a statistical timing framework that takes into account process variations and other nanometer issues is proposed. The DP gives the sensitivity of the circuit performance to a given resistance range of the defect. The efficiency issue when analyzing large circuits is alleviated using stratified sampling techniques to reduce the space of possible analyzed defect locations This methodology is applied to some ISCAS benchmark circuits. The obtained results show the feasibility of the proposed methodology. Measures can be taken for those circuits presenting non-acceptable DP in order to improve the test quality.     

Studies on Conducting Polypyrrole/Graphene Oxide Composites as Supercapacitor Electrode

An electrode material based on polypyrrole (PPy) doped with graphene oxide (GO) sheets was synthesized via in situ polymerization of pyrrole in the presence of GO in various proportions (5% and 10%). The synthesized samples were characterized by Fourier-transform infrared (FTIR) spectroscopy, ultraviolet–visible (UV–vis) absorption spectroscopy, scanning electron microscopy (SEM), transmission electron microscopy (TEM), thermogravimetric analysis (TGA), x-ray diffraction (XRD) analysis, and electrical conductivity measurements. FTIR spectroscopy and XRD revealed the interaction between GO and PPy. The direct-current (DC) electrical conductivity (75.8 S/cm) of the prepared composites was dramatically enhanced compared with pure PPy (1.18 S/cm). High specific capacitance of PPy/GO composite of 421.4 F/g was obtained in the potential range from 0 V to 0.50 V at 2 mA compared with 237.2 F/g for pure PPy by galvanostatic charge–discharge analysis. Incorporation of GO into the PPy matrix has a pronounced effect on the electrical conductivity and electrochemical capacitance performance of PPy/GO nanocomposites.     

A Distortion-Sensitive Seam Carving Algorithm for Content-Aware Image Resizing

As displays become less expensive and are incorporated into more and more devices, there has been an increased focus on image resizing techniques to fill an image to an arbitrary screen size. Traditional methods such as cropping or resampling can introduce undesirable losses in information or distortion in perception. Recently, content-aware image retargeting methods have been proposed (Avidan and Shamir, ACM Trans Graphics 26(3), 2007; Guo et al., IEEE Trans Multimedia 11(5):856–867, 2009; Shamir and Avidan, Commun ACM 52(1), 2009; Simakov et al. 2008; Wolf et al. 2007), which produce exceptional results. In particular, seam carving, proposed by Avidan and Shamir, has gained attention as an effective solution. However, there are many cases where it can fail. In this paper we propose a distortion-sensitive seam carving algorithm for content-aware image resizing that improves edge preservation and decreases aliasing artifacts. In the proposed approach, we use local gradient information along with a thresholding technique to guide the seam selection process and provide a mechanism to halt seam carving when further processing would introduce unacceptable visual distortion in the resized image. Furthermore, anti-aliasing filter is used to reduce the aliasing artifacts caused by seam removal. Experiments have demonstrated superior performance over the current seam carving methods.     

Memory Access Optimized Implementation of Cyclic and Quasi-Cyclic LDPC Codes on a GPGPU

Software based decoding of low-density parity-check (LDPC) codes frequently takes very long time, thus the general purpose graphics processing units (GPGPUs) that support massively parallel processing can be very useful for speeding up the simulation. In LDPC decoding, the parity-check matrix H needs to be accessed at every node updating process, and the size of the matrix is often larger than that of GPU on-chip memory especially when the code length is long or the weight is high. In this work, the parity-check matrix of cyclic or quasi-cyclic (QC) LDPC codes is greatly compressed by exploiting the periodic property of the matrix. Also, vacant elements are eliminated from the sparse message arrays to utilize the coalesced access of global memory supported by GPGPUs. Regular projective geometry (PG) and irregular QC LDPC codes are used for sum-product algorithm based decoding with the GTX-285 NVIDIA graphics processing unit (GPU), and considerable speed-up results are obtained.