Design and implementation of multicasting for multi-channel multi-interface wireless mesh networks

Multicasting is a useful communication method in wireless mesh networks (WMNs). Many applications in WMNs require efficient and reliable multicast communications, i.e., high delivery ratio with low overhead among a group of recipients. In spite of its significance, little work has been done on providing such multicast service in multi-channel WMNs. Traditional multicast protocols for wireless and multi-hop networks tend to assume that all nodes, each of which is equipped with a single interface, collaborate on the same channel. This single-channel assumption is not always true, as WMNs often provide nodes with multiple interfaces to enhance performance. In multi-channel and multi-interface (MCMI) WMNs, the same multicast data must be sent multiple times by a sender node if its neighboring nodes operate on different channels. In this paper, we try to tackle the challenging issue of how to design a multicast protocol more suitable for MCMI WMNs. Our multicast protocol builds multicast paths while inviting multicast members, and tries to allocate the same channel to neighboring members in a bottom-up manner. By unifying fixed channels of one-hop multicast neighbors, the proposed algorithm can improve the performance such as reducing multicast data transmission overhead and delay, while managing a successful delivery ratio. In order to prove such expectation on the performance, we have implemented and evaluated the proposed solution on the real testbed having the maximum 24 nodes, each of which is equipped with two IEEE 802.11a Atheros WLAN cards.     

Tuning the spectrometric properties of white light by surface plasmon effect using Ag nanoparticles in a colour converting light-emitting diode

We report on the spectral tunability of white light by localized surface plasmon (LSP) effect in a colour converting hybrid device made of CdSe/ZnS quantum dots (QDs) integrated on InGaN/GaN blue light-emitting diodes (LEDs). Silver (Ag) nanoparticles (NPs) are mixed with QDs for generating LSP effect. When the plasmon absorption of Ag NPs is synchronized to the QW emission at 448 nm, the NPs selectively absorb the blue light and subsequently enhance the QD emission. Using this energy transfer scheme, the (x, y) chromaticity coordinates of the hybrid white LED was tuned from (0.32, 0.17) to (0.43, 0.26), and thereby generated warm white light emission with correlated colour temperature (CCT) around 1800 K. Moreover, a 47% enhancement in the external quantum efficiency (EQE) was realized.     

All‐Carbon Nanotube‐Based Flexible Field‐Emission Devices: From Cathode to Anode

The fabrication of a flexible field‐emission device (FED) using single‐walled carbon nanotube (SWNT) network films as the conducting electrodes (anode and cathode) and thin multi‐walled CNT/TEOS hybrid films as the emitters is reported. P‐type doping with gold ions and passivation with tetraethylorthosilicate (TEOS) made the SWNT network film highly conductive and environmentally stable, and hence a good alternative to conventional indium tin oxide electrodes. CNT/TEOS hybrid emitters showed high current density, low turn‐on field, and long‐term emission stability, compared with CNT emitters; these characteristics can be attributed to the TEOS sol, acting both as a protective layer surrounding the nanotube tip, and as an adhesive layer enhancing the nanotube adhesion to the substrate. All‐CNT‐based flexible FEDs fabricated by this approach showed high flexibility in field emission characteristics and extremely bright electron emission patterns.     

Fabrication of Ordered Nanostructured Arrays Using Poly(dimethylsiloxane) Replica Molds Based on Three‐Dimensional Colloidal Crystals

Hexagonally arrayed structures of colloidal crystals with uniform surface are a good candidate for master molds to be used in soft lithography. Here, the fabrication of periodically arrayed nanostructures using poly(dimethylsiloxane) (PDMS) molds based on three‐dimensionally (3D) ordered colloidal crystals is reported. A robust, high‐quality 3D colloidal‐crystal master molds is prepared using the colloidal suspension containing a water‐soluble polymer. The surface patterns of the 3D colloidal crystals can then be transferred onto a polymer film via soft lithography, by means of the replication of the surface pattern with PDMS. Various hexagonally arrayed nanostructure patterns can be fabricated, including close‐packed and non‐close‐packed 2D arrays and honeycomb structures by the structural modification of the 3D colloidal‐crystal templates. The replicated hexagonally arrayed structures can also be used as templates for producing colloidal crystals with 2D superlattices.     

Efficient Generation of Scalable Transport Stream for High Quality Service in T‐DMB

We introduce an advanced terrestrial digital multimedia broadcasting (AT‐DMB) system that overcomes the limitation of data transmission rates of T‐DMB by doubling it with the same frequency bandwidth. In this letter, we propose an efficient algorithm which generates a scalable transport stream in AT‐DMB by multiplexing certain types of elementary streams encoded using scalable video coding and an MPEG‐surround audio coder for high‐quality multimedia services.     

An improved sensorless driving method for SRM using a phase-shift circuit technique

This paper presents an improved sensorless driving method for switched reluctance motor (SRM) using a phase-shift circuit technique. The conventional method consists of impressing short voltage pulses during unenergized phases, measuring the phase current pulses, and finding the correlation between the filtered current signals and rotor position. However, the filtering process causes a signal phase delay which varies with motor speed. This delay must be compensated for in providing the sensorless signal which is proper to the rotor position. A solution for this phase delay compensation, based on a simple analog and digital circuit, is proposed in this paper.     

Soluble pentacene thin-film transistor using a high solvent and heat resistive polymeric dielectric with low-temperature processability and its long-term stability

Solution processable organic thin-film transistors (OTFTs) were fabricated using 6,13-bis(triisopropyl-silylethynyl) pentacene (TIPS-pentacene) and low-temperature processable polyimide gate dielectric. The TIPS-pentacene OTFT with the dielectric was found to have a field-effect mobility of 0.15 cm²/Vs, which is comparable to that of OTFT with an inorganic dielectric. The OTFTs with the polyimide dielectric did not show any significant performance degradation as time passed. A field-effect mobility of the OTFTs in 60 days was found to be almost identical to that of pristine OTFT. The combination of TIPS-pentacene and our polyimide gate dielectric can be one of the potential candidates for the fabrication of stable OTFTs for large-area flexible electronics.     

Phase-separated polydimethylsiloxane as a dielectric surface treatment layer for organic field effect transistors

We suggest a novel method for treating the surfaces of dielectric layers in organic field effect transistors (OFETs). In this method, a blend of poly(9,9-dioctylfluorene-alt-bithiophene) (F8T2) and dimethylsiloxane (DMS) with a curing agent is spin coated onto the surface of a dielectric substrate, silicon oxide (SiO₂), and then thermally cured. X-ray photoelectron spectroscopy, contact angle measurements, and morphology analysis were used to show that the hydrophilic DMS layer is preferentially adsorbed on the SiO₂ substrate during the spin coating process. After thermal curing, the bottom DMS layer becomes a hydrophobic PDMS layer. This bottom PDMS layer becomes thinner during curing due to the upward motion of the hydrophobic PDMS molecules. The FET mobility of the cured system was 10^?2 cm²/Vs, which is similar to that of polymeric semiconductors on octadecyltrichlorosilane treated SiO₂ dielectric layers. We also discuss the possibility of using this blend method to increase the air-stability of polymeric semiconductors.     

Performance improvement of TCP in ad hoc networks by mitigating channel contention

In ad hoc networks, the spatial reuse property limits the number of packets which can be spatially transmitted over a path. In standard Transmission Control Protocol (TCP), however, a TCP sender keeps transmitting packets without taking into account this property. This causes heavy contention for the wireless channel, resulting in the performance degradation of TCP flows. Hence, two techniques have been proposed independently in order to reduce the contention. First, a TCP sender utilizes a congestion window limit (CWL), by considering the spatial reuse property. This prevents the TCP sender from transmitting more than CWL number of packets at one time. Second, a delayed ack (DA) strategy is exploited in order to mitigate the contention between the TCP ACK and DATA packets. Recently, although TCP‐DAA (Dynamic Adaptive Acknowledgment) attempts to utilize a CWL‐based DA strategy, TCP‐DAA overlooks a dynamic correlation between these two techniques. This paper, therefore, reveals the dynamic correlation and also proposes a protocol which not only reduces the frequency of the TCP ACK transmissions but also determines a CWL value dynamically, according to network conditions. Simulation studies show that our protocol performs the best in various scenarios, as compared to TCP‐DAA and standard TCP (such as TCP‐NewReno). Copyright © 2009 John Wiley & Sons, Ltd.     

Low-Area Wrapper Cell Design for Hierarchical SoC Testing

System-on-chip (SoC) integrated circuits are designed and fabricated with multiple levels of hierarchy. However, most previous works on wrapper design, test access mechanism optimization and test scheduling did not take care of the hierarchy properly, thus the corresponding test schedules were often invalid for SoCs with hierarchical cores. We propose a low-area wrapper cell design which can treat SoCs with hierarchy properly and allows simultaneous testing of parent and child cores. The proposed cell uses 13%∼23% less area than a recently proposed cell design in equivalent gate count. As a result we achieve up to 21% area reduction for hierarchical ITC ’02 SoCs compared to the most recently proposed designs.