Impact of high-κ dielectric and metal nanoparticles in simultaneous enhancement of programming speed and retention time of nano-flash memory

A methodology to simulate memory structures with metal nanocrystal islands embedded as floating gate in a high-κ dielectric material for simultaneous enhancement of programming speed and retention time is presented. The computational concept is based on a model for charge transport in nano-scaled structures presented earlier, where quantum mechanical tunneling is defined through the wave impedance that is analogous to the transmission line theory. The effects of substrate-tunnel dielectric conduction band offset and metal work function on the tunneling current that determines the programming speed and retention time is demonstrated. Simulation results confirm that a high-κ dielectric material can increase programming current due to its lower conduction band offset with the substrate and also can be effectively integrated with suitable embedded metal nanocrystals having high work function for efficient data retention. A nano-memory cell designed with silver (Ag) nanocrystals embedded in Al₂O₃ has been compared with similar structure consisting of Si nanocrystals in SiO₂ to validate the concept.     

Dirac Cone Spin Polarization of Graphene by Magnetic Insulator Proximity Effect Probed with Outermost Surface Spin Spectroscopy

The effects of the proximity contact with magnetic insulator on the spin‐dependent electronic structure of graphene are explored for the heterostructure of single‐layer graphene (SLG) and yttrium iron garnet Y₃Fe₅O₁₂ (YIG) by means of outermost surface spin spectroscopy using a spin‐polarized metastable He atom beam. In the SLG/YIG heterostructure, the Dirac cone electrons of graphene are found to be negatively spin polarized in parallel to the minority spins of YIG with a large polarization degree, without giving rise to significant changes in the π band structure. Theoretical calculations reveal the electrostatic interfacial interactions providing a strong physical adhesion and the indirect exchange interaction causing the spin polarization of SLG at the interface with YIG. The Hall device of the SLG/YIG heterostructure exhibits a nonlinear Hall resistance attributable to the anomalous Hall effect, implying the extrinsic spin–orbit interactions as another manifestation of the proximity effect.     

Characteristics of planar diodes based on heavily doped GaAs/AlAs superlattices in the terahertz frequency region

Characteristics of ohmic InGaAs contacts in planar diodes based on semiconductor superlattices with a small-area active region (1–10 μm²) are studied. The diodes were formed on the basis of short (18 or 30 periods) heavily doped (10¹⁸ cm⁻³) GaAs/AlAs superlattices with a miniband width of 24.4 meV. The reduced resistance of the ohmic contact was equal to 2×10⁻⁷ Ω cm² at room temperature. It is shown that the properties of fabricated planar diodes make it possible to use these diodes later on in semiconductor devices that operate in the terahertz frequency region in a wide temperature range (4–300 K). __________ Translated from Fizika i Tekhnika Poluprovodnikov, Vol. 38, No. 9, 2004, pp. 1141–1146. Original Russian Text Copyright ? 2004 by Pavel’ev, Demarina, Koshurinov, Vasil’ev, Semenova, Zhukov, Ustinov.     

3GPP LTE‐Assisted Wi‐Fi‐Direct: Trial Implementation of Live D2D Technology

This paper is a first‐hand summary on our comprehensive live trial of cellular‐assisted device‐to‐device (D2D) communications currently being ratified by the standards community for next‐generation mobile broadband networks. In our test implementation, we employ a full‐featured 3GPP LTE network deployment and augment it with all necessary support to provide real‐time D2D connectivity over emerging Wi‐Fi‐Direct (WFD) technology. As a result, our LTE‐assisted WFD D2D system enjoys the required flexibility while meeting the existing standards in every feasible detail. Further, this paper provides an account on the extensive measurement campaign conducted with our implementation. The resulting real‐world measurements from this campaign quantify the numerical effects of D2D functionality on the resultant system performance. Consequently, they shed light on the general applicability of LTE‐assisted WFD solutions and associated operational ranges.     

Thermoelectric Effect Spectroscopy and Photoluminescence of High-Resistivity CdTe:In

Thermoelectric effect spectroscopy and photoluminescence techniques were used to study the defect levels in samples from three crystals of CdTe:In grown by the vertical gradient freeze method. The main goal of the investigation was to study defects, which strongly trap charge carriers or act as recombination centers in order to eliminate them from the technological process. The main difference among detecting and non-detecting samples was the absence of electron traps with a very high capture cross-section and energy 0.6 eV to 0.7 eV, which act as lifetime killers even at low concentrations. Recently published ab initio calculations show a complex of Te antisite and Cd vacancy within this energy range.     

用LED寻找故障的电缆测试仪

本例描述了一个简单的电缆测试仪,它能形象地显示出一根16线电缆束(用于超声辅助驻车系统)的通断问题。一家承包商小批量地生产该线束,因此不适合采用自动化测试仪。为简单起见,用测试信号驱动几只LED,形象化地表示出通断情况。图1中的电路产生一个从0至15的二进制数(0000至1111)。可     

0.18μm铜金属双重镶嵌工艺中空间成像套刻精度分析

由于空间成像套刻(Overlay)技术的预算随集成电路(IC)设计规范的紧缩而吃紧,因此,Overlay测量技术准确度的重要意义也随之提高。通过对后开发(AfterDevelopDI)阶段和后蚀刻(AfterEtchFI)阶段的Overlay测量结果进行比较,研究了0.18μm设计规范下的铜金属双重镶嵌工艺过程中的Overlay准确度。在确保对同一个晶圆进行后开发(DI)阶段和后蚀刻(FI)阶段测试的条件下,我们对成品晶圆的5个工艺层进行了比较。此外,还利用CD-SEM(线宽-扫描电子显微镜)测量了某个工艺层(PolyGate)上的芯片内Overlay,并与采用分割线方法的光学Overlay测量结果进行了比较。发现对芯片内overlay的校准存在着严重的局限性,即在应用CD-SEM时缺乏合适的结构进行Overlay测量。我们还将继续为大家提供定量的比较结果,同时也会向大家推荐组合的CD-SEM测量结构,使其能够被应用到今后的光刻设计中。     

Transient thermo-reflectance measurements of the thermal conductivity and interface resistance of metallized natural and isotopically-pure silicon

The transient thermoreflectance method has been used to measure the thermal conductivity of natural silicon and isotopically-pure silicon-28 layers that are epitaxially grown on natural silicon substrates. The measurements were performed at room temperature for both a low level (10¹⁶) and a higher level (2×10¹⁹) of Boron doping of the epitaxial layers. The results indicate a gain of approximately 55% in the thermal conductivity of Si²⁸ as compared to that of natural Si, at both low and higher levels of doping, and a loss of approximately 19% for both types of silicon due to the higher level of doping.     

Applying Petri Nets to Modeling of Many-Core Processor Self-Testing when Tests are Performed Randomly

Today’s many-core processors are manufactured in inherently unreliable technologies. Massively defective technologies used for production of many-core processors are the direct consequence of the feature size shrinkage in today’s CMOS (complementary metal-oxide-semiconductor) technology. Due to these reliability problems, fault-tolerance of many-core processors becomes one of the major challenges. To reduce the probability of failures of many-core processors various fault tolerance techniques can be applied. The most preferable and promising techniques are the ones that can be easily implemented and have minimal cost while providing high level of processor fault tolerance. One of the promising techniques for detection of faulty cores, and consequently, for performing the first step in providing many-core processor fault tolerance is mutual testing among processor cores. Mutual testing can be performed either in a random manner or according to a deterministic scheduling policy. In the paper we deal with random execution of mutual tests. Effectiveness of such testing can be evaluated through its modeling. In the paper, we have shown how Stochastic Petri Nets can be used for this purpose and have obtained some results that can be useful for developing and implementation of testing procedure in many-core processors.