Fragility assessment of an outrigger structure system based on energy method

Fragility curves development in structures has always been a focus of research interest among structural and earthquake engineers for which the maximum story drift is usually considered as the engineering demand parameter (EDP) known as the conventional approach. This paper aims at calculating the fragility curves of a tall building with outrigger braced system by considering the plastic strain energy as the EDP and compare it with the conventional approach. In addition, the effect of optimizing the position of outriggers on the exceedance probability of the structure under near- and far-fault seismic loadings is investigated in this paper. Fragility curves of this structure in four performance levels including immediate occupancy (IO), life safety (LS), collapse prevention (CP), and instability is extracted based on the conventional method. The fragility curves for the aforementioned performance levels are also extracted based on the plastic strain energy and compared with the conventional approach. The results have demonstrated that optimizing the location of the bracing system would lower the exceedance probability of the structure. Moreover, the exceedance probability of the investigated building with outrigger braced system under far-fault records in various levels is more than that of near-fault records. It is also concluded that the conventional approach would lead to more conservative results compared with the energy approach.     

Extracellular signal-regulated protein kinase/Jun kinase cross-talk underlies vascular endothelial cell growth factor-induced endothelial cell proliferation

Ligand binding to vascular endothelial cell growth factor (VEGF) receptors activates the mitogen-activated protein kinases extracellular signal-regulated kinase (ERK) and c-Jun N-terminal protein kinase (JNK). Possible cross-communication of ERK and JNK effecting endothelial cell (EC) actions of VEGF is poorly understood. Incubation of EC with PD 98059, a specific mitogen-activated protein kinase kinase inhibitor, or transfection with Y185F, a dominant negative ERK2, strongly inhibited VEGF-activated JNK. JNK was also activated by ERK2 expression in the absence of VEGF, inhibited 82% by co-transfection with dominant negative SEK-1, indicating upstream activation of JNK by ERK. VEGF-stimulated JNK activity was also reversed by dominant negative SEK-1. Other EC growth factors exhibited similar cross-activation of JNK through ERK. VEGF stimulated the nuclear incorporation of thymidine, reversed 89% by PD 98059 and 72% by Y185F. Dominant negative SEK-1 or JNK-1 also significantly reduced VEGF-stimulated thymidine incorporation. Expression of wild type Jip-1, which prevents JNK nuclear translocation, inhibited VEGF-induced EC proliferation by 75%. VEGF stimulated both cyclin D1 synthesis and Cdk4 kinase activity, inhibited by PD 98059 and dominant negative JNK-1. Important events for VEGF-induced G1/S progression and cell proliferation are enhanced through a novel ERK to JNK cross-activation and subsequent JNK action.     

Synchronous derived clock and synthesis of low power sequential circuits

Based on analyzing significance of controlling clock in design of low power sequential circuits, this paper proposes a technique that the gating signal is derived from the master latch in a flip-flop to make the derived clock having no glitch and no skew. The design of a decimal counter with half-frequency division shows that by using the synchronous derived clock the counter has lower power dissipation as well as simpler combinational logic. Computer simulation shows 20% power saving.     

Power conscious CAD tools and methodologies: a perspective

Power consumption is rapidly becoming an area of growing concern in IC and system design houses. Issues such as battery life, thermal limits, packaging constraints and cooling options are becoming key factors in the success of a product. As a consequence, IC and system designers are beginning to see the impact of power on design area, design speed, design complexity and manufacturing cost. While process and voltage scaling can achieve significant power reductions, these are expensive strategies that require industry momentum, that only pay off in the long run. Technology independent gains for power come from the area of design for low power which has a much higher return on investment (ROI). But low power design is not only a new area but is also a complex endeavour requiring a broad range of synergistic capabilities from architecture/microarchitecture design to package design. It changes traditional IC design from a two-dimensional problem (Area/performance) to a three-dimensional one (Area/Performance/Power). This paper describes the CAD tools and methodologies required to effect efficient design for low power. It is targeted to a wide audience and tries to convey an understanding of the breadth of the problem. It explains the state of the art in CAD tools and methodologies. The paper is written in the form of a tutorial, making it easy to read by keeping the technical depth to a minimum while supplying a wealth of technical references. Simultaneously the paper identifies unresolved problems in an attempt to incite research in these areas. Finally an attempt is made to provide commercial CAD tool vendors with an understanding of the needs and time frames for new CAD tools supporting low power design     

Power estimation methods for sequential logic circuits

Recently developed methods for power estimation have primarily focused on combinational logic. We present a framework for the efficient and accurate estimation of average power dissipation in sequential circuits. Switching activity is the primary cause of power dissipation in CMOS circuits. Accurate switching activity estimation for sequential circuits is considerably more difficult than that for combinational circuits, because the probability of the circuit being in each of its possible states has to be calculated. The Chapman-Kolmogorov equations can be used to compute the exact state probabilities in steady state. However, this method requires the solution of a linear system of equations of size 2^N where N is the number of flip-flops in the machine. We describe a comprehensive framework for exact and approximate switching activity estimation in a sequential circuit. The basic computation step is the solution of a nonlinear system of equations which is derived directly from a logic realization of the sequential machine. Increasing the number of variables or the number of equations in the system results in increased accuracy. For a wide variety of examples, we show that the approximation scheme is within 1-3% of the exact method, but is orders of magnitude faster for large circuits. Previous sequential switching activity estimation methods can have significantly greater inaccuracies     

Effect of Preheating Inlet Air and Acid Gas on the Performance of Sulfur Recovery Unit—CFD Simulation and Validation

Forschung im Ingenieurwesen - Combustion temperature is a key factor that directly influences the performance of a sulfur recovery unit (SRU); the prevalent low temperatures in...     

A FinFET SRAM cell design with BTI robustness at high supply voltages and high yield at low supply voltages

In this paper, a SRAM cell structure which uses pMOS access transistors and predischarged bitlines is presented. By using the strained pMOS transistor technology, the degradation of the read static noise margin (SNM) at high supply voltages due to the aging, especially in the presence of symmetric stress, is suppressed. In contrast to conventional cell, the write margin of the proposed cell does not degrade considerably at low supply voltages. To assess the efficacy, the proposed cell is compared with conventional cell for two cases of unstrained and strained pMOS. A comparative study is performed using mixed mode device/circuit simulations for a gate length of 22 nm. The results show that the read SNM degradation due to the symmetric aging at the supply voltage of 1 V is about 6% after three years for the proposed strained structure, while degradations are 14%, 12%, and 11% for the unstrained proposed structure, unstrained, and strained conventional structures, respectively. In addition, the proposed cell has both read and write cell sigma yields higher than six for supply voltages ranging from 1 V down to 0.5 V while the other structures have read or write yields less than six at the minimum supply voltage. Through some work function tuning, the cell sigma yields of the other structures reach above six for both read and write while being still lower than those of the proposed structure. Copyright © 2015 John Wiley & Sons, Ltd.