Designing soft-edge flip-flop-based linear pipelines operating in multiple supply voltage regimes

Soft-edge flip-flop (SEFF) based pipelines can improve the performance and energy efficiency of circuits operating in the super-threshold (supply voltage) regime by enabling the opportunistic time borrowing. The application of this technique to the near-threshold regime of operation, however, faces a significant challenge due to large circuit parameter variations that result from manufacturing process imperfections. In particular, delay lines in SEFFs have to be over-designed to provide larger transparency windows to overcome the variation in path delays, which causes them to consume more power. To address this issue, this paper presents a novel way of designing delay lines in SEFFs to have a large enough transparency window size and low power consumption. Two types of linear pipeline design problems using the SEFFs are formulated and solved: (1) designing energy-delay optimal pipelines for the general usage that requires SEFFs to operate in both the near-threshold and super-threshold regimes, and (2) designing minimum energy consumed pipelines for particular use case with a minimum operating frequency constraint. Design methods are presented to derive requisite pipeline design parameters (i.e., depth and sizing of delay lines in SEFFs) and operating conditions (i.e., supply voltage and operating frequency of the design) in presence of process-induced variations. HSPICE simulation results using ISCAS benchmarks demonstrate the efficacy of the presented design methods.     

Flexible Prime‐Field Genus 2 Hyperelliptic Curve Cryptography Processor with Low Power Consumption and Uniform Power Draw

This paper presents an energy‐efficient (low power) prime‐field hyperelliptic curve cryptography (HECC) processor with uniform power draw. The HECC processor performs divisor scalar multiplication on the Jacobian of genus 2 hyperelliptic curves defined over prime fields for arbitrary field and curve parameters. It supports the most frequent case of divisor doubling and addition. The optimized implementation, which is synthesized in a 0.13 μm standard CMOS technology, performs an 81‐bit divisor multiplication in 503 ms consuming only 6.55 μJ of energy (average power consumption is 12.76 μW). In addition, we present a technique to make the power consumption of the HECC processor more uniform and lower the peaks of its power consumption.     

A statistical-based material and process guidelines for design of carbon nanotube field-effect transistors in gigascale integrated circuits

Carbon nanotube field-effect transistors (CNFETs) show great promise as building blocks of future integrated circuits. However, synthesizing single-walled carbon nanotubes (CNTs) with accurate chirality and exact positioning control has been widely acknowledged as an exceedingly complex task. Indeed, density and chirality variations in CNT growth can compromise the reliability of CNFET-based circuits. In this paper, we present a novel statistical compact model to estimate the failure probability of CNFETs to provide some material and process guidelines for the design of CNFETs in gigascale integrated circuits. We use measured CNT spacing distributions within the framework of detailed failure analysis to demonstrate that both the CNT density and the ratio of metallic to semiconducting CNTs play dominant roles in defining the failure probability of CNFETs. Besides, it is argued that the large-scale integration of these devices within an integrated circuit will be feasible only if a specific range of CNT density with an acceptable ratio of semiconducting to metallic CNTs can be adjusted in a typical synthesis process.     

A Highly Efficient Multicore Floating-Point FFT Architecture Based on Hybrid Linear Algebra/FFT Cores

FFT algorithms have memory access patterns that prevent many architectures from achieving high computational utilization, particularly when parallel processing is required to achieve the desired levels of performance. Starting with a highly efficient hybrid linear algebra/FFT core, we co-design the on-chip memory hierarchy, on-chip interconnect, and FFT algorithms for a multicore FFT processor. We show that it is possible to to achieve excellent parallel scaling while maintaining power and area efficiency comparable to that of the single-core solution. The result is an architecture that can effectively use up to 16 hybrid cores for transform sizes that can be contained in on-chip SRAM. When configured with 12MiB of on-chip SRAM, our technology evaluation shows that the proposed 16-core FFT accelerator should sustain 388 GFLOPS of nominal double-precision performance, with power and area efficiencies of 30 GFLOPS/W and 2.66 GFLOPS/mm², respectively.     

Compatibilizers based on polypropylene grafted with itaconic acid derivatives. Effect on polypropylene/polyethylene terephthalate blends

New types of compatibilizers based on functionalized polypropylene (PP) were synthesized by radical melt grafting either with monomethyl itaconate or dimethyl itaconate. The effect of these new modified PP compounds were tested as compatibilizers in PP/polyethylene terephthalate (PET) blends. Blends with compositions 15/85 and 30/70 by weight of PP and PET were prepared in a single‐screw extruder. Morphology of the compatibilized blends revealed a very fine and uniform dispersion of the PP phase as compared with that of noncompatibilized blends of the same composition, leading to improved adhesion between the two phases. Whereas dimethyl itaconate derived agent showed less activity, the monomethyl itaconate parent compound showed an increase of the impact resistance of PET in PP/PET blend. This was attributed to the hydrophilic nature of the monomethyl itaconate part of this compatibilizer. The tensile strength of PET in noncompatibilized blends gradually decreases as the PP content increases, while blends containing functionalized PP exhibited higher values.     

ADSORPTION OF LIGHT HYDROCARBONS ON SPENT SHALE PRODUCED IN A COMBUSTION RETORT

Adsorption isotherms of ethane, propane, and n-butane on two different retorted oil shales were determined gravimetrically at 284.3, 293.7, and 303.2 K. The equilibrium data for these hydrocarbons were correlated with the Langmuir isotherm equation. The equilibrium adsorption data for all the hydrocarbons studied were also correlated by the modified Polanyi potential theory. A single generalized characteristic curve which correlates the equilibrium adsorption data for all three hydrocarbons was obtained by using the ratio of characteristic free energies.     

Leakage Minimization of SRAM Cells in a Dual-$V_t$ and Dual-$T_{rm ox}$ Technology

Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep submicrometer regime. As a result, reducing the subthreshold and tunneling gate leakage currents has become one of the most important criteria in the design of VLSI circuits. This paper presents a method based on dual- V t and dual- T _ox assignment to reduce the total leakage power dissipation of static random access memories (SRAMs) while maintaining their performance. The proposed method is based on the observation that read and write delays of a memory cell in an SRAM block depend on the physical distance of the cell from the sense amplifier and the decoder. Thus, the idea is to deploy different configurations of six-transistor SRAM cells corresponding to different threshold voltage and oxide thickness assignments for the transistors. Unlike other techniques for low-leakage SRAM design, the proposed technique incurs neither area nor delay overhead. In addition, it results in a minor change in the SRAM design flow. The leakage saving achieved by using this technique is a function of the values of the high threshold voltage and the oxide thickness, as well as the number of rows and columns in the cell array. Simulation results with a 65-nm process demonstrate that this technique can reduce the total leakage power dissipation of a 64 times 512 SRAM array by 33% and that of a 32 times 512 SRAM array by 40%.     

Measurement of Consumed Energy Due to the Two-Phase Pressure Drop in a Pulsed Semi-Industrial Column: Effect of Geometry

This article deals with the evaluation of pressure drop and consumption of energy for a steady-state solvent extraction in a horizontal pulsed sieve-plate column, which are important for the design and optimization of the periodic-flow processes for industrial applications. In this study, the pressure drop and the position of loading points are investigated. Moreover, a mathematical evaluation on the energy consumption in the case of a pulsed flow is conducted, and besides the influence of pulsation intensity, the effect of geometrical parameters including the plate spacing and plate-free area is investigated as well. The results of this study are helpful for optimization of column geometry targeted to higher performance and lower energy consumption.     

On the numerical solution of Fredholm integral equations utilizing the local radial basis function method

The current investigation describes a computational technique to solve one- and two-dimensional Fredholm integral equations of the second kind. The method estimates the solution using the discrete collocation method by combining locally supported radial basis functions (RBFs) constructed on a small set of nodes instead of all points over the analysed domain. In this work, we employ the Gauss–Legendre integration rule on the influence domains of shape functions to approximate the local integrals appearing in the method. In comparison with the globally supported RBFs for solving integral equations, the proposed method is stable and uses much less computer memory. The scheme does not require any cell structures, so it is meshless. We also obtain the error analysis of the proposed method and demonstrate that the convergence rate of the approach is high. Illustrative examples clearly show the reliability and efficiency of the new method.     

Interference management for spectral coexistence in a heterogeneous satellite network

With the advent of the fifth generation of mobile radio communication by 2020, there will be many challenges such as increasing service demand with low delay in providing billions of end users called the satellite mobile users. It is expected that terrestrial communication systems will be faced with a dense network having many small cells anywhere and anytime. Therefore, there are some remote regions in the world where terrestrial systems cannot provide any services to end users. Furthermore, because of lack of spectral resources, it is very important that the spectrum is shared between satellite systems and terrestrial equipment by a suitable solution to interference management. In this paper, a heterogeneous satellite network that includes low earth orbit (LEO) satellite constellation and terrestrial equipment is proposed to provide low delay services. In this type of structure, interference management based on transmission power control between LEO satellite systems and mobile users is very important for obtaining high throughput. Moreover, in order to mitigate interference, transmission power control is shown based on noncooperative Stackelberg game under many subgames through pricing‐based algorithm and convex optimization method. Finally, the simulation results show that the performance of this study's system model will be improved through the proposed algorithm.