涤纶复合丝（POY＋DTY）的研发

DTY和POY网络复合丝是以聚酯直纺生产的两种不同规格的POY丝为原料,通过对加弹机进行适当改造,利用不同的加工路线,使一股POY丝经过加捻后形成DTY,再与另一股POY丝网络合股形成包芯复合丝.该复合丝利用POY丝和DTY丝的收缩差异和染色差异等不同风格特性,使得布面形成一种具有雪花状的色丁效果.该复合丝属于差别化纤维,是国家鼓励发展的项目,它具有优良的吸湿排汗性能和弹性保暖性能,是保暖内衣的首选面料,市场前景广阔.     

井冈山水厂设计体会

阐述水厂设计中对水厂规模、水源地、净水厂位置及净水工艺的确定过程，根据原水的特点，通过分析对无阀滤池进行改良。     

顺丁橡胶后处理新型交替运输机

在顺丁橡胶后处理生产线上，用处行开发的新型交替运输取代原有运输机。试用结果表明，采用新型交替运输机后，胶块的导向到位率由７０％提高到９８％；减轻了劳动强度，提出了生产开工率，运行周期可达１ａ以上。     

电子聚合物基体碳纳米管复合材料研究进展

电子聚合物是一种新型的功能材料，碳纳米管具有优异的力学性能和独特的电学性能等，是聚合物基体复合材料的理想增强体，按不同电子聚合物基体类型进行了归纳，评述了电子聚合物基体碳纳米管复合材料的制备，性能和应用等情况。     

Modeling of current-voltage characteristics for strained andlattice matched HEMT's on InP substrate using a variational chargecontrol model

A model for the calculation of the current-voltage characteristics of strained In_0.52Al_0.48As/In_xGa_1-xAs on InP substrate High Electron Mobility Transistors (HEMT's), based on a variational charge control model, is presented. A polynomial fit of the two-dimensional electron gas (2DEG) density is used for the calculation of the current-voltage characteristics. The effect of strain is introduced into the 2DEG density versus gate voltage relation. Very good agreement between the calculated and measured I-V characteristics was obtained. In addition, our results show that, for an indium mole fraction of the In_xGa_1-xAs channel in the range 0.53-0.60, increasing the indium mole fraction lowers the threshold voltage and hence increases the drain current at the same gate bias     

开放、交流与凝聚--广州大学城广外学生活动中心设计

2003年夏天，广州大学城广州外语外贸大学一期项目的单体设计在相当短的设计周期中紧张地铺开。     

适用于高速长途DWDM系统的色散管理线路

对于高速长途密集波分复用（DWDM）传输，必需采用各种各样的色散补偿、色散管理技术，其中，交替使用正负色散光纤构成色散管理线路（DML）是可行的解决方案之一，在国际上已经取得显著进展，正成为人们关注的焦点，国内在这方面的研究报道还少见.文章以高速长途DWDM系统对传输线路的性能要求为基础，综述了有代表性的3种不同类型的DML的特点和最新进展。     

Modular and rapid testing of SOCs with unwrapped logic blocks

Extensive research has been carried out for test planning of core-based system-on-a-chip devices. Most of the prior work assumes that all of the embedded cores are wrapped for test purpose. However, some designs may contain user-defined logic or cores that cannot be wrapped due to area constraints or timing violations. This paper discusses how these unwrapped logic blocks can be tested rapidly by adapting the TestRail architecture, which uses only the test control mechanism and the test instructions available through the IEEE 1500 standard for embedded core test. A new test scheduling algorithm, which facilitates a concurrent test of both unwrapped logic blocks and IEEE 1500-wrapped cores, is proposed, and experiments show that it outperforms a previous approach when the available number of tester channels and/or the number of unwrapped logic blocks are small.