The concert queueing game: to wait or to be late

We introduce the concert (or cafeteria) queueing problem: A finite but large number of customers arrive into a queueing system that starts service at a specified opening time. Each customer is free to choose her arrival time (before or after opening time), and is interested in early service completion with minimal wait. These goals are captured by a cost function which is additive and linear in the waiting time and service completion time, with coefficients that may be class dependent. We consider a fluid model of this system, which is motivated as the fluid-scale limit of the stochastic system. In the fluid setting, we explicitly identify the unique Nash-equilibrium arrival profile for each class of customers. Our structural results imply that, in equilibrium, the arrival rate is increasing up until the closing time where all customers are served. Furthermore, the waiting queue is maximal at the opening time, and monotonically decreases thereafter. In the simple single class setting, we show that the price of anarchy (PoA, the efficiency loss relative to the socially optimal solution) is exactly two, while in the multi-class setting we develop tight upper and lower bounds on the PoA. In addition, we consider several mechanisms that may be used to reduce the PoA. The proposed model may explain queueing phenomena in diverse settings that involve a pre-assigned opening time.     

Providing secure execution environments with a last line of defense against Trojan circuit attacks

Integrated circuits (ICs) are often produced in foundries that lack effective security controls. In these foundries, sophisticated attackers are able to insert malicious Trojan circuits that are easily hidden in the large, complex circuitry that comprises modern ICs. These so-called Trojan circuits are capable of launching attacks directly in hardware, or, more deviously, can facilitate software attacks. Current defense against Trojan circuits consists of statistical detection techniques to find such circuits before product deployment. The fact that statistical detection can result in false negatives raises the obvious questions: can attacks be detected post-deployment, and is secure execution nonetheless possible using chips with undetected Trojan circuits? In this paper we present the Secure Heartbeat And Dual-Encryption (SHADE) architecture, a compiler–hardware solution for detecting and preventing a subset of Trojan circuit attacks in deployed systems. Two layers of hardware encryption are combined with a heartbeat of off-chip accesses to provide a secure execution environment using untrusted hardware. The SHADE system is designed to complement pre-deployment detection techniques and to add a final, last-chance layer of security.     

Recommendation engine based on derived wisdom for more similar item neighbors

Information Systems and e-Business Management - Collaborative filtering (CF) is a popular and widely accepted recommendation technique. CF is an automated form of word-of-mouth communication...     

Compiler-assisted power optimization for clustered VLIW architectures

Clustered VLIW architectures solve the scalability problem associated with flat VLIW architectures by partitioning the register file and connecting only a subset of the functional units to a register file. However, inter-cluster communication in clustered architectures leads to increased leakage in functional components and a high number of register accesses. In this paper, we propose compiler scheduling algorithms targeting two previously ignored power-hungry components in clustered VLIW architectures, viz., instruction decoder and register file.We consider a split decoder design and propose a new energy-aware instruction scheduling algorithm that provides 14.5% and 17.3% benefit in the decoder power consumption on an average over a purely hardware based scheme in the context of 2-clustered and 4-clustered VLIW machines. In the case of register files, we propose two new scheduling algorithms that exploit limited register snooping capability to reduce extra register file accesses. The proposed algorithms reduce register file power consumption on an average by 6.85% and 11.90% (10.39% and 17.78%), respectively, along with performance improvement of 4.81% and 5.34% (9.39% and 11.16%) over a traditional greedy algorithm for 2-clustered (4-clustered) VLIW machine.     

Compact modeling of amorphous‐silicon thin‐film transistors with BSIM3

Abstract— A novel approach of modeling a‐Si:H TFTs with the industry‐standard BSIM3 compact model is presented. The described approach defines the a‐Si:H TFT drain current and terminal charges as explicit functions of terminal voltages using a minimum set of BSIM3 parameters. The set of BSIM3 parameters is chosen based on the electrical and physical characteristics of the a‐Si:H TFT and their values extracted from measured data. By using the selected BSIM3 model parameters, the a‐Si:H TFT is simulated inside SPICE to fit the simulated I‐V and C‐V curves with the measured results. Finally, the extracted BSIM3 model is validated by simulating the kickback voltage effect in an AMLCD pixel array.     

Shape Morphing-Based Control of Robotic Visual Servoing

We present an approach for controlling robotic interactions with objects, using synthetic images generated by morphing shapes. In particular, we attempt the problem of positioning an eye-in-hand robotic system with respect to objects in the workspace for grasping and manipulation. In our formulation, the grasp position (and consequently the approach trajectory of the manipulator), varies with each object. The proposed solution to the problem consists of two parts. First, based on a model-based object recognition framework, images of the objects taken at the desired grasp pose are stored in a database. The recognition and identification of the grasp position for an unknown input object (selected from the family of recognizable objects) occurs by morphing its contour to the templates in the database and using the virtual energy spent during the morph as a dissimilarity measure. In the second step, the images synthesized during the morph are used to guide the eye-in-hand system and execute the grasp. The proposed method requires minimal calibration of the system. Furthermore, it conjoins techniques from shape recognition, computer graphics, and vision-based robot control in a unified engineering amework. Potential applications range from recognition and positioning with respect to partially-occluded or deformable objects to planning robotic grasping based on human demonstration.     

FireFly: a cross-layer platform for real-time embedded wireless networks

We propose a cross-layer approach with tightly-coupled time synchronization for real-time support and predictable lifetime in battery-operated sensor networks. Our design spans a sensor hardware platform with hardware-based global time synchronization, a TDMA link layer protocol with collision-free multi-hop support and node scheduling algorithms for maximum concurrency and streaming. Our dual-radio sensor platform, FireFly, features an IEEE 802.15.4 transceiver and supports global time synchronization indoors by using an AM radio carrier-current method and an atomic clock receiver for outdoors. A TDMA-based link protocol, RT-Link, leverages the hardware for fixed and mobile nodes with a near-optimal and predictable node lifetime of over 2 years. It outperforms comparable sensor network link protocols such as B-MAC and S-MAC in terms of end-to-end latency and throughput and node lifetime across all duty cycle ratios. Operating over RT-Link is MAX, a scheduling framework which offers optimal transmission concurrency and bandwidth management for networks with regular structure. Through analysis and experiments we show that global time sync is a robust, economical and scalable alternative to in-band software-based techniques. To illustrate the capabilities and flexibility of our platform, we describe our experiences with two-way voice streaming over multiple hops. We have deployed a 42-node network with sub-100 μs synchronization accuracy in the NIOSH experimental coal mine for people-tracking and voice communication.

Compiler-assisted energy optimization for clustered VLIW processors

Clustered architecture processors are preferred for embedded systems because centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption. Although clustering helps by improving the clock speed, reducing the energy consumption of the logic, and making the design simpler, it introduces extra overheads by way of inter-cluster communication. This communication happens over long global wires having high load capacitance which leads to delay in execution and significantly high energy consumption. Inter-cluster communication also introduces many short idle cycles, thereby significantly increasing the overall leakage energy consumption in the functional units. The trend towards miniaturization of devices (and associated reduction in threshold voltage) makes energy consumption in interconnects and functional units even worse, and limits the usability of clustered architectures in smaller technologies. However, technological advancements now permit the design of interconnects and functional units with varying performance and power modes. In this paper, we propose scheduling algorithms that aggregate the scheduling slack of instructions and communication slack of data values to exploit the low-power modes of functional units and interconnects. Finally, we present a synergistic combination of these algorithms that simultaneously saves energy in functional units and interconnects to improves the usability of clustered architectures by achieving better overall energy–performance trade-offs. Even with conservative estimates of the contribution of the functional units and interconnects to the overall processor energy consumption, the proposed combined scheme obtains on average 8% and 10% improvement in overall energy–delay product with 3.5% and 2% performance degradation for a 2-clustered and a 4-clustered machine, respectively. We present a detailed experimental evaluation of the proposed schemes. Our test bed uses the Trimaran compiler infrastructure.     

Laser micro-welding of aluminum and copper with and without tin foil alloy

In this paper continuous laser welding of two dissimilar materials, aluminum and copper, was investigated. The aluminum and the copper utilized were Al3003-H14 and Cu110-H00, respectively. Two different sets of samples were laser welded; one in which a filler material, tin foil alloy (S-bond 220), was sandwiched between the aluminum and the copper and another set in which the aluminum and copper were directly welded without any filler. The foil alloy was utilized to enhance the compatibility of the two metals; aluminum and copper, reducing the brittleness of the intermetallic compound that may form and, subsequently, enhance the mechanical properties. The welding was carried out using an IPG 500 SM fiber laser. The length of the laser joint produced was 20 mm and the width was about 200 μm. The strength of the joint was evaluated by conducting the lap shear stress test. Samples in which filler foil was used exhibited a better performance in the lap shear stress test (an average of 780 N) than the samples without tin foil (an average of 650 N). The improvement in the lap shear test could be attributed to the positive effects of the filler on enhancing the compatibility of the intermetallic compound formed via diffusion. The fracture surface of both types of joints (with and without filler) was characterized using scanning electron microscope equipped with energy-dispersive X-ray (EDAX). To understand the failure initiation and propagation of the samples under tension, a finite element (FE) model was developed for the samples created with no filler material. The failure mechanism predicted from the FE model matches reasonably well with the experimental observations from EDAX analysis.     

A three-axis SOI accelerometer sensing with both in-plane and vertical comb electrodes

A three-axis capacitive accelerometer based on silicon-on-insulator is designed and fabricated. In the accelerometer, totally eight groups of capacitors are compactly arranged around an octagonal proof mass. The four groups of capacitors along orthogonal direction with in-plane comb electrodes detect XY acceleration, while the other four groups of capacitors along diagonal direction with vertical comb electrodes detect Z acceleration. Measurements of in-plane and vertical motion by the respective in-plane and vertical comb electrodes enable direct detection for all the three axes with differential capacitive sensing scheme. For the fabricated accelerometer in the size of 4 × 4 mm², the capacitance sensitivities of in-plane and out-of-plane accelerometers are 145.3 and 9.1 fF/g, respectively.