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91.
We outline a hybrid analog-digital scheme for computing with three important features that enable it to scale to systems of large complexity: First, like digital computation, which uses several one-bit precise logical units to collectively compute a precise answer to a computation, the hybrid scheme uses several moderate-precision analog units to collectively compute a precise answer to a computation. Second, frequent discrete signal restoration of the analog information prevents analog noise and offset from degrading the computation. And, third, a state machine enables complex computations to be created using a sequence of elementary computations. A natural choice for implementing this hybrid scheme is one based on spikes because spike-count codes are digital, while spike-time codes are analog. We illustrate how spikes afford easy ways to implement all three components of scalable hybrid computation. First, as an important example of distributed analog computation, we show how spikes can create a distributed modular representation of an analog number by implementing digital carry interactions between spiking analog neurons. Second, we show how signal restoration may be performed by recursive spike-count quantization of spike-time codes. And, third, we use spikes from an analog dynamical system to trigger state transitions in a digital dynamical system, which reconfigures the analog dynamical system using a binary control vector; such feedback interactions between analog and digital dynamical systems create a hybrid state machine (HSM). The HSM extends and expands the concept of a digital finite-state-machine to the hybrid domain. We present experimental data from a two-neuron HSM on a chip that implements error-correcting analog-to-digital conversion with the concurrent use of spike-time and spike-count codes. We also present experimental data from silicon circuits that implement HSM-based pattern recognition using spike-time synchrony. We outline how HSMs may be used to perform learning, vector quantization, spike pattern recognition and generation, and how they may be reconfigured.  相似文献   
92.
This paper first identifies some of the key concerns about the techniques and algorithms developed for parallel model checking; specifically, the inherent problem with load balancing and large queue sizes resultant in a static partition algorithm. This paper then presents a load balancing algorithm to improve the run time performance in distributed model checking, reduce maximum queue size, and reduce the number of states expanded before error discovery. The load balancing algorithm is based on generalized dimension exchange (GDE). This paper presents an empirical analysis of the GDE based load balancing algorithm on three different supercomputing architectures—distributed memory clusters, Networks of Workstations (NOW) and shared memory machines. The analysis shows increased speedup, lower maximum queue sizes and fewer total states explored before error discovery on each of the architectures. Finally, this paper presents a study of the communication overhead incurred by using the load balancing algorithm, which although significant, does not offset performance gains.  相似文献   
93.
This is the second of two papers describing a procedure for the three-dimensional nonlinear time-history analysis of steel-framed buildings. An overview of the procedure and the theory for the panel zone element and the plastic hinge beam element are presented in part I. In this paper, the theory for an efficient new element for modeling beams and columns in steel frames called the elastofiber element is presented, along with four illustrative examples. The elastofiber beam element is divided into three segments—two end nonlinear segments and an interior elastic segment. The cross sections of the end segments are subdivided into fibers. Associated with each fiber is a nonlinear hysteretic stress-strain law for axial stress and strain. This accounts for coupling of nonlinear material behavior between bending about the major and minor axes of the cross section and axial deformation. Examples presented include large deflection of an elastic cantilever beam, cyclic loading of a cantilever beam, pushover analysis of a 20-story steel moment-frame building to collapse, and strong ground motion analysis of a two-story unsymmetric steel moment-frame building.  相似文献   
94.
95.
Device characteristics of double heterostructure lasers with Al0.4Ga0.6As confinement layers and GaAs0.99Sb0.01active layers are presented. Average emission wavelengths have been increased from 0.87 μm for undoped active layers to 0.88 μm for2 times 10^{17}cm-3Ge doped active layers with a "wash" melt preceding the growth of the active layer and to 0.89 μ for1 times 10^{18}cm-3Mg doped active layers grown following a "wash" melt. Threshold currents for lasers from 21 wafers are examined for several growth conditions and compared with Al0.08Ga0.92As active layer devices. Device resistance, external quantum efficiency, device degradation, and pulsed and CW threshold currents as a function of temperature are also discussed.  相似文献   
96.
A review of the nature of solar radiation and the spectral distribution of its energy is presented. The attenuation of solar radiation by scattering and absorption and the effects of atmospheric pollutants on radiation attenuation with an estimate of the long-term effects of pollutants is discussed.  相似文献   
97.
Recent changes in the U.S. electric power markets have contributed to volatility in hourly prices and loads. In this paper we consider the position of the electric power retailer who typically contracts with suppliers and end-users and must provide future load requirements to the suppliers. As part of this energy supply chain, the retailer is faced with great uncertainty in both market prices as well as end-user loads. Based on actual data for the PJM market covering Pennsylvania, New Jersey, and Maryland, we develop a probabilistic optimization model to optimize the net profits for the retailer for a forecast time horizon (typically one or more hours) given the cumulative performance in previous time periods (hours). The resulting model is formulated as a mixed integer linear program with binary variables due to the disjunctive nature of certain forward load estimation bandwidth tolerance constraints. In addition, we also provide an existence result to this optimization model. Lastly, we present a numerical example of the optimization model to validate its workings and provide some insight into model sensitivities.  相似文献   
98.
The Internet is rapidly improving our ability to support information flows across global supply chains. However, the business impact of these IT investments depends not just on the information flows supported by such systems, but also on other non-information related characteristics of the supply chain. It is the complex interplay among these characteristics that results in business performance, or lack thereof. In order to better understand the business impact of IT investments in the supply chain, we are motivated to examine the ‘physics’ of supply chain structures. By physics, we mean the performance patterns inherent in its informational and physical characteristics. Using the systems dynamics methodology, we model basic information and physical characteristics of supply chains and examine their impact on some common measures of performance. Experiments with the models suggest that, in addition to information delays, physical delays also have a major impact on the stability of supply chains, as well as on operating cost. Moreover, the tradeoff between chain stability and responsiveness appears to be nonlinear, suggesting that a small compromise in responsiveness may yield larger gains in stability. Multi-tier chains appear to be less ‘stiff’ in responding to demand fluctuations, implying that their information systems must be specifically designed to overcome this structural tendency. These results have managerial implications in terms of designing the information and physical structure of a supply chain as well as for its operation.  相似文献   
99.
A scheme for creating metal-coated vertical mirrors in silicon, along with an integrated transparent package lid for assembling, packaging, and testing microelectromechanical systems (MEMS) devices is presented. Deep reaction ion etching (DRIE) method described here reduces the loading effect and maintains a uniform etch rate resulting in highly vertical structures. A novel self-masking lithography and liftoff process was developed to ensure that the vertical mirrors undergo uniform metallization while leaving a transparent window for optical probing. Front side of a Si wafer was shallow-etched using DRIE to define an eventual optical window. This surface was then anodically bonded to a Pyrex wafer. Backside Si was then patterned to define thin channels around the optical window. These channels were vertically etched using DRIE, after which the unattached portions of the window region were removed. Negative photoresist was spun on the remaining vertical structures and the stack was exposed from the Pyrex side using Si structures as a self-mask. Subsequent metal sputtering and liftoff results in the metallized top and mirror sidewalls while leaving a clear window. These integrated mirrors and lids are then bonded to the active MEMS mirrors. Various processes and results are illustrated with an example of packaged corner cube retroreflectors (CCRs)  相似文献   
100.
A fast-settling adaptive calibration technique is presented that makes phase noise cancelling DeltaSigma fractional-N PLLs practical for the low reference frequencies commonly used in wireless communication systems. The technique is demonstrated as an enabling component of a 2.4 GHz ISM band CMOS PLL IC with a 730 kHz bandwidth, a 12 MHz reference, and an on-chip loop filter. In addition to the adaptive calibration technique, the IC incorporates a dynamic charge pump biasing technique to reduce power dissipation. The worst-case phase noise of the IC is -101 dBc/Hz and -124 dBc/Hz at 100 kHz and 3 MHz offsets, respectively, and the adaptive phase noise cancellation technique has a worst-case settling time of 35 mus . The IC is implemented in 0.18 CMOS technology. It measures 2.2 x 22 mm2 and its core circuitry consumes 20.9 mA from a 1.8 V supply.  相似文献   
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