Interactions between the physical layer and upper layers in wireless networks

The physical layer in wireless networks has characteristics that profoundly influence the operation of a network and the resulting performance. Interactions between the physical layer and higher layers are complex and intricate, and cannot be understood without taking the details of operation at all layers into account. Furthermore, these interactions often lead to unexpected and undesirable effects.

We illustrate these effects by studying four different scenarios: (i) the impact of channel fading on the quality of voice over IP for communication between two devices, (ii) the quality of streaming video in the case of two interfering wireless networks, (iii) the impact of physical layer parameters and path loss on throughput in a multihop scenario, and (iv) the impact of channel variability on the performance of routing and applications in a real test-bed.     

Measurements of the heat release rate integral in turbulent premixed stagnation flames with particle image velocimetry

A new definition of turbulent consumption speed is proposed in this work that is based on the heat release rate integral, rather than the mass burning rate integral. Its detailed derivation and the assumptions involved are discussed in a general context that applies to all properly defined reaction progress variables. The major advantage of the proposed definition is that it does not require the thin-flame assumption, in contrast to previous definitions. Experimental determination of the local turbulent displacement speed, SD, and the local turbulent consumption speed, SC, is also demonstrated with the particle image velocimetry technique in three turbulent premixed stagnation flames. The turbulence intensity of these flames is of the same order of the laminar burning velocity. Based on the current data, a model equation for the local mean heat release rate is proposed. The relationship between SD and SC is discussed along with a possible modeling approach for the turbulent displacement speed.     

n-Type silicon quantum dots and p-type crystalline silicon heteroface solar cells

Heteroface devices have been realized by depositing phosphorus-doped silicon (Si) quantum dots (QDs) (n-type) on a p-type crystalline silicon substrate. To compare the quantum confinement effect, different sizes (3, 4, 5, and 8±1 nm) of Si QD were fabricated, whose optical energy bandgaps are in the ranges of 1.3–1.65 eV. The electrical and photovoltaic properties of heterojunction devices were characterized by illuminated and dark I–V measurements, C–V measurements, and spectral response measurements. The diodes showed a good rectification ratio of 5×10⁶ for 4 nm Si QDs at the bias voltage of ±1.0 V at 298 K. The ideality factor and junction built-in potential deduced from current–voltage (I–V) and capacitance–voltage (C–V) plots are 1.86 and 0.847 V for 3 nm QD device, respectively. From the illuminated IV characteristics, the open circuit voltages were 556, 540, 512, and 470 mV for mean QD diameters 3, 4, 5, and 8±1 nm, respectively. Temperature-dependant dark I–V measurements suggest that the carrier transport in the devices is controlled by recombination in the space-charge region. This study indicates the silicon QDs can be good candidates for all-silicon tandem solar cells.     

Collaborative design environment between ECAD and MCAD engineers in high-tech products development

In order to make more competitive electronic products, major electronics companies struggle to design products with a thin shape and complex convergence functionalities without any lead-time and cost increase. Also, the development mission of a project is changed continuously to catch up with the competitor’s products in a short time and the importance of aesthetic design is getting bigger and bigger in these days. In many cases, shape changes bring the electrical layout changes of a notebook computer main board and vise versa. Those development environmental changes make the engineers harder and harder and require more collaboration between electrical and mechanical engineers to reduce development time and design errors occur from early design stage. In this paper, a collaborative design environment consists of a web-based project management system and automated printed circuit board (PCB) generation and validation system is proposed. The web system is used for project management and design data exchange including electrical CAD (ECAD) data and related technical documents between ECAD and mechanical CAD (MCAD) engineers. By using this project management web portal, engineers can share the design information with design change history. ECAD data in Intermediate Data Format can be automatically validated in 2D domain while sending the ECAD data via web system. To generate a full 3D quality product model with PBA in MCAD side, an automated 3D PCB generation and assembly clearance checking module is developed.     

Surface deformation of amorphous silicon thin film on elastomeric substrate

Stiff thin layers on compliant substrates can generate various surface structures using equi-biaxial stress caused by large thermal expansion rate differences. We investigated the detailed understanding on the evolution of self-assembled wrinkle patterns of ultra-thin amorphous silicon (a-Si) layers on polydimethylsiloxane substrate. It turns out that the generation of various wrinkle patterns depends on the position of their orientation, film thicknesses, mechanical properties of the a-Si films, and the amount of pre-strain. The various self-assembled patterns include one-dimensional wavy patterns, randomly ordered two-dimensional structured patterns, and herringbone structures. The self-assembled wrinkles can be characterized by the wavelength and amplitude of the distinct structures: the amplitudes of the various patterns increase as the amount of pre-strain increases, while the wavelengths remain constant within our experimental ranges. The experimental results of the wavelengths and amplitudes for the wavy structured patterns of 270-nm-thick a-Si layer are in good agreement with the theoretical solutions of the single crystalline silicon (c-Si) model, which implies that the theoretical modeling of the deformation of c-Si film can be expandable to the case of a-Si film deformations.     

Effect of ball size and powder loading on the milling efficiency of a laboratory-scale wet ball mill

Alumina powder was wet-milled by zirconia balls with varying diameter at varying rotation speed, and the resultant particle size of the milled powder was analyzed. At a given rotation speed, there exists an optimum ball size to yield minimum particle size of alumina. The optimum ball diameter decreases as the rotation speed increases. This result has been interpreted in light of the competition between the reduced kinetic energy of the smaller balls (a negative source for milling efficiency) and the increased number of contact points of the smaller balls (a positive source), which yields the optimum ball diameter at an intermediate size. As the rotation speed increases, kinetic energy of the balls increases, which, in turn, shifts the optimum ball size toward a smaller value. As the powder loading increases from 1 to 35 g at a given rotation speed and ball size, the milling efficiency decreases monotonically.     

Nanometer-scale oxide thin film transistor with potential for high-density image sensor applications

The integration of electronically active oxide components onto silicon circuits represents an innovative approach to improving the functionality of novel devices. Like most semiconductor devices, complementary-metal-oxide-semiconductor image sensors (CISs) have physical limitations when progressively scaled down to extremely small dimensions. In this paper, we propose a novel hybrid CIS architecture that is based on the combination of nanometer-scale amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) and a conventional Si photo diode (PD). With this approach, we aim to overcome the loss of quantum efficiency and image quality due to the continuous miniaturization of PDs. Specifically, the a-IGZO TFT with 180 nm gate length is probed to exhibit remarkable performance including low 1/f noise and high output gain, despite fabrication temperatures as low as 200 °C. In particular, excellent device performance is achieved using a double-layer gate dielectric (Al?O?/SiO?) combined with a trapezoidal active region formed by a tailored etching process. A self-aligned top gate structure is adopted to ensure low parasitic capacitance. Lastly, three-dimensional (3D) process simulation tools are employed to optimize the four-pixel CIS structure. The results demonstrate how our stacked hybrid device could be the starting point for new device strategies in image sensor architectures. Furthermore, we expect the proposed approach to be applicable to a wide range of micro- and nanoelectronic devices and systems.     

Ridge formation and removal via annealing in exfoliated graphene

It is well known that graphene is a very promising material due to its excellent physical, chemical, and thermal properties. Previously, ridges in graphene on a substrate were found in epitaxial graphene on a SiC substrate. It was found in this study that ridges can be made on a graphene layer via mechanical exfoliation on a sapphire substrate, and that ridges can be created or removed through heating and cooling. Due to the difference of the thermal-expansion coefficients of the substrate and graphene, it can be said that thermal cycling causes compressive strain, which is released by forming ridges. Annealing was carried out in a vacuum chamber within the pressure range of 10(-3)-10(-6) Torr and at 900-1100 degrees C. To analyze the shapes and mechanical properties of the ridges, Raman spectroscopy and AFM measurement were performed. It was found that the ridges can be extended by defect as a nucleation center, and the graphene layer can be folded along the preexisting ridge during heating and cooling.     

Carbon nanotube field effect transistors with suspended graphene gates

Novel field effect transistors with suspended graphene gates are demonstrated. By incorporating mechanical motion of the gate electrode, it is possible to improve the switching characteristics compared to a static gate, as shown by a combination of experimental measurements and numerical simulations. The mechanical motion of the graphene gate is confirmed by using atomic force microscopy to directly measure the electrostatic deflection. The device geometry investigated here can also provide a sensitive measurement technique for detecting high-frequency motion of suspended membranes as required, e.g., for mass sensing.