A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector

We describe a 40-Gbit/s-class clock and data recovery (CDR) circuit with an extremely wide pull-in range. A Darlington-type voltage-controlled oscillator (VCO) is newly designed to cover the STM-256/OC-768 full-rate-clock frequencies with a wide frequency margin. We also describe a new lock detector using an exclusive-NOR gate. The CDR IC was fabricated using InP/InGaAs HBTs. Error-free operation and wide eye opening were confirmed for 40-, 43-, and 45-Gbit/s PRBS with a word length of 2/sup 31/ - 1. We attached a frequency search and phase control (FSPC) circuit to the chip as a new frequency acquisition aid, and this allows the CDR circuit to pull in throughout a 39-45-Gbit/s range. The peak-to-peak and rms jitter of the recovered clock were 3.6 and 0.48 ps, respectively.     

PMD compensation in optical coherent single carrier transmission using frequency-domain equalisation

The transmission performance of optical single-carrier (SC) transmission using frequency-domain equalisation (FDE) to counter polarisation mode dispersion (PMD) is evaluated. 25 Gbit/s coherent optical SC transmission using FDE (CO-SC-FDE) is demonstrated in the presence of a significant amount of differential group delay (DGD). The results show that CO-SC-FDE compensates for the influence of the 125 ps DGD; the OSNR penalty is 0.81 dB.     

Two-dimensional ensemble Monte Carlo calculation of pulse responsesof submicrometer GaAs metal-semiconductor-metal photodetectors

Pulse responses of top-illuminated GaAs metal-semiconductor-metal photodetectors (MSM PDs) are evaluated by using a two-dimensional ensemble Monte Carlo technique. Fundamental assumptions and the model used for the evaluation are detailed. Pulsewidths for MSM PDs are presented as functions of the gap length between metal electrodes and the photon energy of optical pulses. It is also shown that reducing the thickness of the absorption region is very effective for shortening the pulsewidth of MSM PDs     

An improved procedure of electron microscopic in situ hybridization for detecting adenovirus DNA

Electron microscopic in situ hybridization (EM-ISH) is a useful method in determining the localization of a specific nucleic acid at the ultrastructural level. Since the EM-ISH protocol includes many steps, no standard protocol for EM-ISH is available yet. In this study, we optimized quantitatively the critical conditions with respect to embedding resin, nucleic acid labeling and hybridization reaction time, by using adenovirus-infected cells as the indicator cells. The optimal detection of an adenovirus-specific nucleic acid was obtained by overnight hybridization reaction on sections embedded in Lowicryl K4M resin. Random-primed-labeled probes improved the reactivity. At least 60% of virus particles in paracrystalline arrays was found to contain viral DNA. These arrays in adenovirus-infected cells are useful in evaluating quantitatively the efficiency of protocols of EM-ISH.     

A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning

A 16 Mb embedded DRAM macro in a fully CMOS logic compatible 90 nm process with a low noise core architecture and a high-accuracy post-fabrication tuning scheme has been developed. Based on the proposed techniques, 61% improvement of the sensing accuracy is realized. Even with the smallest 5 fF/cell capacitance, a 322 MHz random-cycle access while 32 ms data retention time which contributes to save the data retention power down to 60 /spl mu/W are achieved.     

An 80-Gb/s optoelectronic delayed flip-flop IC using resonanttunneling diodes and uni-traveling-carrier photodiode

This paper describes an 80-Gb/s optoelectronic delayed flip-flop (D-FF) IC that uses resonant tunneling diodes (RTDs) and a uni-traveling-carrier photodiode (UTC-PD). A circuit design that considers the AC currents passing through RTDs and UTC-PD is key to boosting circuit operation speed. A monolithically fabricated IC operated at 80 Gb/s with a low power dissipation of 7.68 mW. The operation speed of 80 Gb/s is the highest among all reported flip-flops. To clarify the maximum operation speed, we analyze the factors limiting circuit speed. Although the bandwidth of UTC-PD limits the maximum speed of operation to 80 Gb/s at present, the circuit has the potential to offer 100-Gb/s-class operation     

A differential photoconductive AND gate with Be-dopedlow-temperature-grown InGaAs-InAlAs MQW MSM-PD's

A novel photoconductive AND gate that overcomes the problems of: 1) the long tail of photoconductive switches and 2) signal leakage via switch capacitance (signal feedthrough) is proposed. We use Be-doped low-temperature (LT)-grown InGaAs-InAlAs MQW metal-semiconductor-metal photodetectors (MSM-PD's) to get a shorter turn-off time and propose a differential AND gate to cancel the signal feedthrough. A comparison between LT-grown MSM-PD's and those fabricated by ion implantation shows that the LT-grown ones are ultrafast with a full width at half maximum of 5.3 ps and are suitable for low-bias operation. It is experimentally confirmed that the differential AND gate completely cancels the signal feedthrough in the picosecond region. The differential AND gate: with the LT MSM-PD's achieves return-to-zero (RZ) 20 Gb/s AND operation     

A super-dynamic flip-flop circuit for broad-band applications up to24 Gb/s utilizing production-level 0.2-μm GaAs MESFETs

This paper describes a novel dynamic flip-flop (FF) circuit that can operate 30% faster than conventional clocked inverter-type FFs. A new wideband clock buffer is introduced to cover the FF operation range. An 8- to 24-Gb/s decision circuit and a 9- to 26-GHz 1/2 frequency divider were developed utilizing production-level 0.2-μm GaAs MESFET technology     

A design technique for a high-gain, 10-GHz class-bandwidth GaAsMESFET amplifier IC module

A design procedure is proposed for a high-gain and wideband IC module, using stability analysis and a unified design methodology for ICs and packages. A multichip structure is developed using stability analysis and the requirements for stable operation are determined for each IC chip, package, and interface condition between them. Furthermore, to reduce the parasitic influences, several improvements in the interface and package design are clarified, such as wideband matching and LC resonance damping. IC design using effective feedback techniques for enlarging the bandwidth are also presented. The ICs are fabricated using 0.2-μm GaAs MESFET IC technology. To verify the validity of these techniques, an equalizer IC module for 10-Gb/s optical communication systems was fabricated, achieving a gain of 36 dB and a bandwidth of 9 GHz     

0.5-μm 3.3-V BiCMOS standard cells with 32-kilobyte cache andten-port register file

BiCMOS standard cell macros, including a 0.5-W 3-ns register file, a 0.6-W 5-ns 32-kbyte cache, a 0.2-W 3-ns table look-aside buffer (TLB), and a 0.1-W 3-ns adder, are designed with a 0.5-μm BiCMOS technology. A supply voltage of 3.3 V is used to achieve low power consumption. Several BiCMOS/CMOS circuits, such as a self-aligned threshold inverter (SATI) sense amplifier and an ECL HIT logic are used to realize high-speed operation at the low supply voltage. The performance of the BiCMOS macros is verified using a fabricated test chip