Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property

This paper presents a statistical leakage estimation method for FinFET devices considering the unique width quantization property. Monte Carlo simulations show that the conventional approach underestimates the average leakage current of FinFET devices by as much as 43% while the proposed approach gives a precise estimation with an error less than 5%. Design example on subthreshold circuits shows the effectiveness of the proposed method.     

Buffering global interconnects in structured ASIC design

Structured ASICs present an attractive alternative to reducing design costs and turnaround times in nanometer designs. As with conventional ASICs, such designs require global wires to be buffered. However, via-programmable designs must prefabricate and preplace buffers in the layout. This paper proposes a novel and accurate statistical estimation technique for distributing prefabricated buffers through a layout. It employs Rent's rule to estimate the buffer distribution required for the layout, so that an appropriate structured ASIC may be selected for the design. Experimental results show that the buffer distribution estimation is accurate and economic, and that a uniform buffer distribution can maintain a high degree of regularity in design and shows a good timing performance, comparable with nonuniform buffer distribution.     

BDD decomposition for delay oriented pass transistor logic synthesis

We address the problem of synthesizing pass transistor logic (PTL), with the specific objective of delay reduction, through binary decision diagram (BDD) decomposition. The decomposition is performed by mapping the BDD to a network flow graph, and then applying the max-flow min-cut technique to bipartition the BDD optimally under a cost function that measures the delay and area of the decomposed implementations. Experimental results obtained by running our algorithm on the set of ISCAS'85 benchmarks show a 31% improvement in delay and a 30% improvement in area, on an average, as compared to static CMOS implementations for XOR intensive circuits, while in case of arithmetic logic unit and control circuits that are NAND intensive, improvements over static CMOS are small and inconsistent.     

Guest Editors' Introduction: New Dimensions in 3D Integration

Although various forms of 3D fabrication technology have existed for a few decades, only in recent years have researchers developed highly integrated 3D design technologies that are potentially manufacturable and economically feasible. Several companies are already marketing 3D structures built by wafer stacking, where the distance between the 3D layers on a wafer are on the order of the wafer thickness. But 3D technology must also surmount several challenges, such as exploiting the design space to build high-performance systems and architectures to gain the fullest advantage achievable. The articles in this special issue highlight these advances and challenges, providing an excellent snapshot of the state of 3D technology as it stands today.     

Book Review: An Assay of Biochips [review of two books: Design Automation Methods and Tools for Microfluidics-Based Biochips (Chakrabarty, K. and Zeng, J., eds.) and BioMEMS (Urban, G.A., ed.)

This is an integrated review of two related books, Design Automation Methods and Tools for Microfluidics-Based Biochips (edited by Krishnendu Chakrabarty and Jun Zeng) and BioMEMS (edited by Gerald A. Urban). Both books include contributions from several authors on topics related to their areas of expertise. Together, they provide a good introduction to the field of biochips. All in all, both books are well written and constitute excellent sources for a first, or second, look at this field.     

Analysis and optimization of power grids

As the complexity of power and ground networks increases, methods for efficient analysis and aggressive optimization of these networks become essential. Here, the authors describe efficient hierarchical methods for analyzing distribution networks. To optimize the networks, the authors call for techniques that reduce noise on the power grid, including topology selection, wire widening, and decoupling-capacitance insertion, combined with supply, signal, and clock network codesign.     

Book Reviews: Plumbing the Depths of Leakage

A review of Leakage in Nanometer CMOS Technologies, edited by Siva G. Narendra and Anantha Chandrakasan (Springer, 2006).     

Temperature-Aware Placement for SOCs

Dramatic rises in the power consumption and integration density of contemporary systems-on-chip (SoCs) have led to the need for careful attention to chip-level thermal integrity. High temperatures or uneven temperature distributions may result not only in reliability issues, but also timing failures, due to the temperature-dependent nature of chip time-to-failure and delay, respectively. To resolve these issues, high-quality, accurate thermal modeling and analysis, and thermally oriented placement optimizations, are essential prior to tapeout. This paper first presents an overview of thermal modeling and simulation methods, such as finite-difference time domain, finite element, model reduction, random walk, and Green-function based algorithms, that are appropriate for use in placement algorithms. Next, two-dimensional and three-dimensional thermal-aware placement algorithms such as matrix-synthesis, simulated annealing, partition-driven, and force directed are presented. Finally, future trends and challenges are described.     

Interleaving buffer insertion and transistor sizing into a singleoptimization

This work presents strategies to insert buffers in a circuit, combined with gate sizing, to achieve better power delay and area-delay tradeoffs. The purpose of this work is to examine how combining a sizing algorithm with buffer insertion will help us achieve better area delay or power-delay tradeoffs, and to determine where and when to insert buffers in a circuit, The delay model incorporates placement-based information and the effect of input slew rates on gate delays. The results obtained by using the new method are significantly better than the results given by merely using a TILOS-like gate sizing algorithm alone, as is illustrated by several area delay tradeoff curves shown in this paper     

Designing "Vary" Good Circuitry

Statistical Analysis and Optimization for VLSI: Timing and Power, by Ashish Srivastava, Dennis Sylvester, and David Blaauw (Springer, 2005, ISBN 0-38-725738-1, 279 pp., $129). Variation-tolerant techniques based on statistical design have been the focus of intense research over the past few years. This book is the first detailed survey of developments in this field; it is an excellent resource for anyone interested in learning about the topic, as well as a practitioner or researcher seeking a quick reference. Users of statistical analysis and optimization CAD tools will find it invaluable because it provides the background required to separate the wheat from the chaff.