SATPOLY: a self-aligned tungsten on polysilicon process for CMOSVLSI applications

The use of complementarily doped n⁺ and p⁺ polysilicon has been proposed for future generations of CMOS technology. The implementation of this technology requires low-resistance shunts both to reduce the overall resistance of the gate level interconnections and to short out the polysilicon p-n junctions. A process in which tungsten is chosen to provide the low-resistance shunts, with the necessary gate sidewall spacers formed before the selective deposition of tungsten, is described. A nonselective tungsten deposition process, originally developed explicitly for the implementation of direct tungsten gate MOS technology, is a key step in the formation of the spacers in the SATPOLY (self-aligned tungsten on polysilicon) process. The work function stability and the adhesion of the tungsten-polysilicon double-layer structure as a function of the polysilicon glue layer thickness have also been investigated     

Two-dimensional thermal oxidation of silicon. II. Modeling stresseffects in wet oxides

For pt.I see ibid., vol.ED-34, p.1008-17 (May 1987). The authors propose that the stress from two-dimensional oxide deformation affects the kinetic parameter in the Deal-Grove model (1965). In particular, the viscous stress associated with the nonuniform deformation of the oxide is identified as the fundamental force of retardation. In this model, the stress normal to the Si-SiO₂ interface reduces the surface reaction rate in both convex and concave surfaces, whereas the stress in the bulk of the oxide (compressive for concave and tensile for convex surfaces) is responsible for the thinner oxides on the concave structures. The model is described by a simplified mathematical formulation made possible by the symmetry in cylindrical structures. Comparisons with experimental data, possible applications, and limitations of the model are also discussed     

Study on hydrogenation of polysilicon thin film transistors by ionimplantation

Hydrogenation of polysilicon (poly-Si) thin film transistors (TFT's) by ion implantation has been systematically studied. Poly-Si TFT performance was dramatically improved by hydrogen ion implantation followed by a forming gas anneal (FGA). The threshold voltage, channel mobility, subthreshold swing, leakage current, and ON/OFF current ratio have been studied as functions of ion implantation dose and FGA temperature. Under the optimized conditions (H⁺ dose of 5×10¹⁵ cm^-2 and FGA temperature at 375°C), NMOS poly-Si TFT's fabricated by a low temperature 600°C process have a mobility of ~27 cm ²/V·s, a threshold voltage of ~2 V, a subthreshold swing of ~0.9 V/decade, and an OFF-state leakage current of ~7 pA/μm at V_DS=10 V. The avalanche induced kink effect was found to be reduced after hydrogenation     

The effect of fluorine in silicon dioxide gate dielectrics

The effect of post-oxide-growth fluorine incorporation in gate dielectrics is reported. Fluorine was introduced through ion implantation into polysilicon and diffused into the gate oxide, as indicated by SIMS measurements. No great decrease in the breakdown field was observed, although a decrease in charge-to-breakdown was seen. Interface characteristics also improved with medium to high doses of fluoride. High doses were found to grow additional oxide. NMOS FETs showed increased immunity to hot-electron-induced stress. These results are explained by a model wherein fluorine bonds to silicon, and the displaced oxygen grows the additional oxide     

Polycrystalline silicon-germanium thin-film transistors

The fabrication of p- and n-channel MOS thin-film transistors (TFT's) in polycrystalline silicon-germanium (poly-Si_1-xGe _x) films is described, and their electrical characteristics are presented. Various technological issues are then addressed in order to provide direction for further work in optimizing the fabrication process. The initial devices fabricated in this work exhibit well behaved electrical characteristics; enhanced performance is expected to accompany improvements in the crystallization and defect-passivation processes. Compared to a poly-Si TFT technology, an optimized poly-Si _1-xGe_x TFT technology may ultimately be able to provide a lower-temperature, shorter-time processing capability at little expense to device performance and it is therefore promising for large-area electronics applications     

Electrical properties of heavily doped polycrystallinesilicon-germanium films

The electrical properties of polycrystalline silicon-germanium (poly-Si_1-xGe_x) films with germanium mole fractions up to 0.56 doped by high-dose ion implantation are presented. The resistivity of heavily doped p-type (P⁺) poly-Si_1-x Ge_x is much lower than that of comparably doped poly-Si, because higher levels of boron activation and higher hole mobilities are achieved in poly-Si_1-xGe_x. The resistivity of heavily doped n-type (N⁺) poly-S_1-xGe_x is similar to that of comparably doped poly-Si for x<0.45; however, it is considerably higher for larger Ge mole fractions due to significant reductions in phosphorus activation. Lower temperatures (~500°C), as well as lower implant doses, are sufficient to achieve low resistivities in boron-implanted poly-Si_1-xGe_x films, compared to poly-Si films. The work function of P⁺ poly-Si_1-xGe_x decreases significantly (by up to ~0.4 Volts), whereas the work function of N⁺ poly-Si_1-xGe_x decreases only slightly, as Ge content is increased. Estimates of the energy bandgap of poly-Si_1-xGe_x show a reduction (relative to the bandgap of poly-Si) similar to that observed for unstrained single-crystalline Si_1-xGe_x for a 26% Ge film, and a reduction closer to that observed for strained single-crystalline Si _1-xGe_x for a 56% Ge film. The electrical properties of poly-Si_1-xGe_x make it a potentially favorable alternative to poly-Si for P⁺ gate-material applications in metal-oxide-semiconductor technologies and also for p-channel thin-film transistor applications     

A new methodology for design of BiCMOS gates and comparison withCMOS

A gate comparison methodology is presented to accurately compare the performance of an arbitrary BiCMOS logic gate with a pure CMOS gate. The concept of the sizing plane (SP) is introduced as a geometrical framework in which the gate comparison methodology is represented. The sizing plane is also shown to be an elegant platform to represent the constraints and tradeoffs in BiCMOS gate design and this is demonstrated by an example for a 1-μm BiCMOS technology. To illustrate the comparison methodology, BiCMOS and CMOS gates are fabricated in a 2-μm BiCMOS technology. The measured performance results are presented and interpreted using the sizing plane. A technology comparison methodology is proposed that predicts the relative performance of a BiCMOS versus a pure CMOS implementation of any arbitrary block of digital logic     

A wideband polarization reconfigurable isosceles trapezoidal monopole antenna

In this article, a polarization reconfigurable isosceles trapezoidal monopole antenna for the circular polarization (CP) is presented. A trapezoidal monopole and the ground plane are on the same side of the dielectric substrate. The monopole is excited by a reconfigurable T‐shaped 50 Ω microstrip feed line and reconfigurable vertical slots are incorporated in the ground plane to realize switchable wideband CP. For the different switching states of the p‐i‐n diodes, linear polarization, left‐handed and right handed CP can be achieved in the boresight direction (+z direction). The antenna prototype is fabricated and tested. The measured reflection coefficient bandwidth (|S11| < ?10 dB) is 31.2% (2.13 ‐ 2.91 GHz) and axial ratio bandwidth (axial ratio < 3 dB) is 22% (2.18 ‐ 2.72 GHz) for the CP. The measured reflection coefficient bandwidth is 18.56% (2.15 ‐ 2.59 GHz) for linear polarization.     

A Borda count for collective sentiment analysis

A method for detecting potential violations of integrity constraints of concurrent transactions running under snapshot isolation (SI) is presented. Although SI provides a high level of isolation, it does not, by itself, ensure that all integrity constraints are satisfied. In particular, while current implementations of SI enforce all internal integrity constraints, in particular key constraints, they fail to enforce constraints implemented via triggers. One remedy is to turn to serializable SI (SSI), in which full serializability is guaranteed. However, SSI comes at the price of either a substantial number of false positives, or else a high cost of constructing the full direct serialization graph. In this work, a compromise approach, called constraint-preserving snapshot isolation (CPSI), is developed, which while not guaranteeing full serializability, does guarantee that all constraints, including those enforced via triggers, are satisfied. In contrast to full SSI, CPSI requires testing concurrent transactions for conflict only pairwise, and thus involves substantially less overhead while providing a foundation for resolving conflicts via negotiation rather than via abort and restart. As is the case with SSI, CPSI can result in false positives. To address this, a hybrid approach is also developed which combines CPSI with a special version of SSI called CSSI, resulting in substantially fewer false positives than would occur using either approach alone.     

Preparation and characterization of chemically deposited lead sulphide thin films

A chemical method for the deposition of PbS thin films has been developed using appropriate amounts of lead acetate, thioacetamide and triethanolamine. The thickness of the films are in the range 0.3 to 1 m. The films are polycrystalline and p-type. The dependence of the film thickness as a function of the bath parameters has also been studied and explained on the basis of ion-ion condensation theory.