Microscopic foci of urachal carcinoma in an incidentally detected urachal cyst: a case report

A 33-year-old man who had been treated for chronic prostatitis was diagnosed to have urachal cysts by transabdominal ultrasonography. Cystoscopy revealed protuberance at the dome of the bladder. Computerized tomography scan and magnetic resonance imaging showed the mass to be mostly cystic but partly solid. Resection of the urachal cysts and partial cystectomy were performed. Histopathologically, most cysts had a normal cylindrical epithelium with retention of mucinous substance. However, several small cysts contained epithelial cells resembling tubulo-villous adenoma and showing mitotic figures. This case was concluded as urachal carcinoma detected in its very early stage.     

TEM characterization of Co-Al-O nano-granular TMR film

Co-Al-O film was fabricated using the reactive r.f. magnetron sputtering technique. A maximum magnetoresistance (MR) of approximately 7% was established through optimizing the sputter deposition conditions such as sputter power and gas flow rate. TEM characterization of the film revealed a nano-granular structure that consisted of ferromagnetic grains with grain diameters on the order of several nm together with non-magnetic grain boundary layers with the thickness on the order of less than 1 nm. The large MR was attributed to electron tunneling thorough this very thin grain boundary layer between individual ferromagnetic grains.     

1.5%-/spl Delta/ athermal arrayed-waveguide grating multi/demultiplexer with very low loss groove design

We describe a compact 1.5%-/spl Delta/ athermal silica-based 100-GHz-spacing 16-channel arrayed-waveguide grating (AWG) multi/demultiplexer with a modified groove design for a very low excess loss. We propose new approaches for modifying the shape of the grooves and the arrayed waveguides and optimize the shape modifications for 1.5%-/spl Delta/ waveguides. By employing this modified groove design, we greatly reduced the groove excess loss from 1.9 to 0.4 dB in the 1.5%-/spl Delta/ athermal AWG.     

Development of thermoelectric module based on dense Ca3Co4O9 and Zn0.98Al0.02O legs

Ca₃Co₄O₉ (p-type) and Zn_0.98Al_0.02O (n-type) pellets were prepared by conventional sintering (CS) and Spark Plasma sintering (SPS) starting from the oxides. The best p-type sample was SPS Ca₃Co₄O₉ obtained from pre-sintered pellets, with electrical conductivity σ = 144 S/cm and Seebeck coefficient S = 172 μV/K at 800 °C, while thermal conductivity κ = 2.00 W/m×K and figure of merit ZT = 0.23. The best n-type sample was CS Zn_0.98Al_0.02O showing σ = 83 S/cm and S = ?268 μV/K at 800 °C, while = 5.03 W/m×K and ZT = 0.127. The output power of a module based on SPS Ca₃Co₄O₉ and CS Zn_0.98Al_0.02O legs was 2.26 mW (with T = 500 °C, ΔT = 248 °C).     

Reduction of Second-Order Temperature Dependence of Athermal AWG With Resin-Filled Groove by Pressure Control

In this letter, we have developed a novel technique for improving the temperature stability of an athermal silica-based arrayed-waveguide grating with a resin-filled groove. We compensated for the residual second-order temperature dependence of the passband wavelength using the pressure-induced refractive index change in a resin inserted into the optical paths. Pressure control under the temperature variation was achieved by using a structure composed of an optical fiber piston and bimetal actuators. We demonstrated that the passband wavelength variation was successfully reduced from 0.080 to 0.025 nm in a -40degC - 85degC temperature range, without any insertion loss increase or spectral change.     

A 146-mm/sup 2/ 8-gb multi-level NAND flash memory with 70-nm CMOS technology

An 8-Gb multi-level NAND Flash memory with 4-level programmed cells has been developed successfully. The cost-effective small chip has been fabricated in 70-nm CMOS technology. To decrease the chip size, a one-sided pad arrangement with compacted core architecture and a block address expansion scheme without block redundancy replacement have been introduced. With these methods, the chip size has been reduced to 146 mm/sup 2/, which is 4.9% smaller than the conventional chip. In terms of performance, the program throughput reaches 6 MB/s at 4-KB page operation, which is significantly faster than previously reported and very competitive with binary Flash memories. This high performance has been achieved by the combination of the multi-level cell (MLC) programming with write caches and with the program voltage compensation technique for neighboring select transistors. The read throughput reaches 60 MB/s using 16I/O configuration.     

The effect of ulinastatin on CFU-C colony formation in mouse myelocyte cultures

The mixture of 5'-guanylylimidodiphosphate (Gpp(NH)p)/EDTA/NaCl has been used to delineate low-affinity conditions for agonists binding to G-protein-linked receptors. The effects of this mixture on [3H]RX821002 (2-methoxyidazoxan) binding to alpha2-adrenoceptors were evaluated in different tissues. The density of alpha2-adrenoceptors in the presence of the mixture was 11, 78 and 60% higher in human cortex (predominant alpha2A), human caudate (alpha2A + alpha2C) and rat kidney (alpha2A + alpha2B), respectively, than in its absence. In rat kidney, masking of alpha2B-adrenoceptors by ARC239 (2-[2-[4-(o-methoxyphenyl)-piperazin-1-yl]-ethyl]-4,4-dimethyl-1,3 -(2H,4H)-isoquinolindione) (50 nM) or masking of alpha2A-adrenoceptors by BRL44408 (2-[2H-(1-methyl-1,3-dihydroisoindole)methyl]-4,5-dihydroimidaz ole) (100 nM) demonstrated that the increase was in the alpha2B-adrenoceptor but not in the alpha2A-adrenoceptor subtype.     

Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding

This paper describes a heterogeneous multi-core processor (HMCP) architecture that integrates general-purpose processors (CPUs) and accelerators (ACCs) to achieve exceptional performance as well as low-power consumption for the SoCs of embedded systems. The memory architectures of CPUs and ACCs were unified to improve programming and compiling efficiency. Advanced audio codec-low complexity (AAC-LC) stereo audio encoding was parallelized on a heterogeneous multi-core having homogeneous processor cores and dynamically reconfigurable processor (DRP) ACC cores in a preliminary evaluation of the HMCP architecture. The performance evaluation revealed that 54times AAC encoding was achieved on the chip with two CPUs at 600 MHz and two DRPs at 300 MHz, which achieved encoding of an entire CD within 1- 2 min.