Complexity reduction of digital filters using shift inclusive differential coefficients

We present a graph theoretical methodology that reduces the implementation complexity of the multiplication of a constant vector and a scalar. The complexity of implementation is defined as the required amount of computations like additions. The proposed approach is called minimally redundant parallel (MRP) optimization and is mainly presented in a finite impulse response (FIR) filtering framework to obtain a low-complexity multiplierless implementation. The key idea is to expand the design space using shift inclusive differential coefficients (SIDCs) together with computation reordering using a graph theoretic approach to obtain maximal computation sharing. The problem is formulated using a graph in which vertices and edges represent coefficients and computational cost (number of resources). The multiplierless solution is obtained by solving a set cover problem on the vertices in the graph. A simple polynomial run time algorithm based on a greedy approach is presented. The proposed approach is compared with common-subexpression elimination to show slightly better results and is combined with it for further reduction of complexity. Simulation results show that 50-60% complexity reduction is achieved by only applying the MRP algorithm, and 70% complexity reduction is obtainable by combining it with common-subexpression elimination under a delay constraint of two or three.     

Numerical and experimental analysis of nonradiative dielectric guide modulator and mixer at Ka band

This letter describes the numerical analysis of an on/off modulator and a single-ended mixer in nonradiative dielectric (NRD) guide configuration at Ka band. Currently, only experimental results are available for such structures. A shunt mounted diode switch in NRD guide configuration is analyzed using the finite element method (FEM) in conjunction with linear circuit simulation. A novel mixer is similarly analyzed using FEM and harmonic balance analysis. The results obtained from numerical analysis are compared with measured results. It is demonstrated that some counter-intuitive experimental results can be explained through numerical analysis.     

Affective Learning — A Manifesto

The use of the computer as a model, metaphor, and modelling tool has tended to privilege the 'cognitive' over the 'affective' by engendering theories in which thinking and learning are viewed as information processing and affect is ignored or marginalised. In the last decade there has been an accelerated flow of findings in multiple disciplines supporting a view of affect as complexly intertwined with cognition in guiding rational behaviour, memory retrieval, decision-making, creativity, and more. It is time to redress the imbalance by developing theories and technologies in which affect and cognition are appropriately integrated with one another. This paper describes work in that direction at the MIT Media Lab and projects a large perspective of new research in which computer technology is used to redress the imbalance that was caused (or, at least, accentuated) by the computer itself.     

Anticipation of nitrided oxides electrical thickness based on XPS measurement

Plasma nitridation of thermally grown oxide films has proven to be an excellent gate dielectric in meeting the electrical requirements of the 65 nm node. As the 65 nm device performance is very sensitive to both physical thickness and nitrogen dose of these dielectric films, it is highly desirable to predict the electrical properties of such films. We present a simple physical model to forecast the capacitance-equivalent thickness (CET) of nMOS devices for 65 nm technology. The model is based on the total nitrogen dose and the dielectric physical thickness, both given by in-line X-ray photoelectron spectroscopy (XPS) measurement of the plasma nitrided gate dielectric. This model uses an estimated gate oxide dielectric constant, the gate depletion capacitance and the inversion layer capacitance. A good correlation is obtained between calculated and measured CET for plasma nitrided oxides from 19 to 30 Å CET and for a large range of incorporated nitrogen doses.     

EEG complexity as a measure of depth of anesthesia for patients

A new approach for quantifying the relationship between brain activity patterns and depth of anesthesia (DOA) is presented by analyzing the spatio-temporal patterns in the electroencephalogram (EEG) using Lempel-Ziv complexity analysis. Twenty-seven patients undergoing vascular surgery were studied under general anesthesia with sevoflurane, isoflurane, propofol, or desflurane. The EEG was recorded continuously during the procedure and patients' anesthesia states were assessed according to the responsiveness component of the observer's assessment of alertness/sedation (OAA/S) score. An OAA/S score of zero or one was considered asleep and two or greater was considered awake. Complexity of the EEG was quantitatively estimated by the measure C(n), whose performance in discriminating awake and asleep states was analyzed by statistics for different anesthetic techniques and different patient populations. Compared with other measures, such as approximate entropy, spectral entropy, and median frequency, C(n) not only demonstrates better performance (93% accuracy) across all of the patients, but also is an easier algorithm to implement for real-time use. The study shows that C(n) is a very useful and promising EEG-derived parameter for characterizing the (DOA) under clinical situations.     

ISDN applications at Tenneco Gas

The evolution from analog to integrated services digital network (ISDN) telecommunication services at Tenneco Gas and the features of its telephone system are described. The results of implementing ISDN in data operations are examined. The benefits of ISDN for Tenneco are briefly summarized     

Computation sharing programmable FIR filter for low-power and high-performance applications

This paper presents a programmable digital finite-impulse response (FIR) filter for high-performance and low-power applications. The architecture is based on a computation sharing multiplier (CSHM) which specifically targets computation re-use in vector-scalar products and can be effectively used in the low-complexity programmable FIR filter design. Efficient circuit-level techniques, namely a new carry-select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. A 10-tap programmable FIR filter was implemented and fabricated in CMOS 0.25-/spl mu/m technology based on the proposed architectural and circuit-level techniques. The chip's core contains approximately 130 K transistors and occupies 9.93 mm/sup 2/ area.