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61.
Residential segregation is an inherently spatial phenomenon as it measures the separation of different types of people within a region. Whether measured with an explicitly spatial index, or a classic aspatial index, a region’s underlying spatial properties could manifest themselves in the magnitude of measured segregation. In this paper we implement a Monte Carlo simulation approach to investigate the properties of four segregation indices in regions built with specific spatial properties. This approach allows us to control the experiment in ways that empirical data do not. In general we confirm the expected results for the indices under various spatial properties, but some unexpected results emerge. Both the Dissimilarity Index and Neighborhood Sorting Index are sensitive to region size, but their spatial counterparts, the Adjusted Dissimilarity Index and Generalized Neighborhood Sorting Index, are generally immune to this problem. The paper also lends weight to concerns about the downward pressure on measured segregation when multiple neighborhoods are grouped into a single census tract. Finally, we discuss concerns about the way space is incorporated into segregation indices since the expected value of the spatial indices tested is lower than their aspatial counterparts.  相似文献   
62.
An effective solution to automate information extraction from Web pages is represented by wrappers. A wrapper associates a Web page with an XML document that represents part of the information in that page in a machine-readable format. Most existing wrapping approaches have traditionally focused on how to generate extraction rules, while they have ignored potential benefits deriving from the use of the schema of the information being extracted in the wrapper evaluation. In this paper, we investigate how the schema of extracted information can be effectively used in both the design and evaluation of a Web wrapper. We define a clean declarative semantics for schema-based wrappers by introducing the notion of (preferred) extraction model, which is essential to compute a valid XML document containing the information extracted from a Web page. We developed the SCRAP (SChema-based wRAPper for web data) system for the proposed schema-based wrapping approach, which also provides visual support tools to the wrapper designer. Moreover, we present a wrapper generalization framework to profitably speed up the design of schema-based wrappers. Experimental evaluation has shown that SCRAP wrappers are not only able to successfully extract the required data, but also they are robust to changes that may occur in the source Web pages.  相似文献   
63.
A novel classifier is introduced to overcome the limitations of the k-NN classification systems. It estimates the posterior class probabilities using a local Parzen window estimation with the k-nearest-neighbour prototypes (in the Euclidean sense) to the pattern to classify. A learning algorithm is also presented to reduce the number of data points to store. Experimental results in two hand-written classification problems demonstrate the potential of the proposed classification system.  相似文献   
64.
Entanglement of formation and concurrence for mixed states   总被引:1,自引:0,他引:1  
We review some results on analytical computations of the measures for quantum entanglement: entanglement of formation and concurrence. We introduce some estimations of the lower bounds for the entanglement of formation in bipartite mixed states, and of lower bounds for the concurrence in bipartite and tripartite systems. The results on lower bounds for the concurrence are also generalized to arbitrary multipartite systems.  相似文献   
65.
To meet both flexibility and performance requirements, particularly when implementing high-end real-time image/video processing algorithms, the paper proposes to combine the application specific instruction-set processor (ASIP) paradigm with the reconfigurable hardware one. As case studies, the design of partially reconfigurable ASIP (r-ASIP) architectures is presented for two classes of algorithms with widespread diffusion in image/video processing: motion estimation and retinex filtering. Design optimizations are addressed at both algorithmic and architectural levels. Special processor concepts used to trade-off performance versus flexibility and to enable new features of post-fabrication configurability are shown. Silicon implementation results are compared to known ASIC, DSP or reconfigurable designs; the proposed r-ASIPs stand for their better performance–flexibility figures in the respective algorithmic class.
Luca FanucciEmail:

Sergio Saponara   got the Laurea degree, cum laude, and the Ph.D. in Electronic Engineering from the University of Pisa in 1999 and 2003, respectively. In 2002, he was with IMEC, Leuven (B), as Marie Curie Research Fellow. Since 2001, he collaborates with Consorzio Pisa Ricerche-TEAM in Pisa. He is senior researcher at the University of Pisa in the field of VLSI circuits and systems for telecom, multimedia, space and automotive applications. He is co-author of more than 80 scientific publications. He holds the chair of electronic systems for automotive and automation at the Faculty of Engineering. Michele Casula   received the Laurea degree in Electronic Engineering from the University of Pisa in 2005. Since 2006, he is pursuing a Ph.D. degree in Information Engineering at the same university. His current interests involve VLSI circuits design, computer graphics, and Network-on-Chips. Luca Fanucci    received the Laurea degree and the Ph.D. degree in Electronic Engineering from the University of Pisa in 1992 and 1996, respectively. From 1992 to 1996, he was with ESA/ESTEC, Noordwijk (NL), as a research fellow. From 1996 to 2004, he was a senior researcher of the Italian National Research Council in Pisa. He is Professor of Microelectronics at the University of Pisa. His research interests include design methodologies and hardware/software architectures for integrated circuits and systems. Prof. Fanucci has co-authored more than 100 scientific publications and he holds more than ten patents.  相似文献   
66.
There is increasing demand to extend Object RequestBroker (ORB) middleware to support distributed applications withstringent real-time requirements. However, conventional ORB implementations,such as CORBA ORBs, exhibit substantial priority inversion andnon-determinism, which makes them unsuitable for applicationswith deterministic real-time requirements. This paper providestwo contributions to the study and design of real-time ORB middleware.First, it illustrates empirically why conventional ORBs do notyet support real-time quality of service. Second, it evaluatesconnection and concurrency software architectures to identifystrategies that reduce priority inversion and non-determinismin real-time CORBA ORBs. The results presented in this paperdemonstrate the feasibility of using standard OO middleware likeCORBA to support certain types of real-time applications overthe Internet.  相似文献   
67.
This paper presents novel algorithmic and architectural solutions for real-time and power-efficient enhancement of images and video sequences. A programmable class of Retinex-like filters, based on the separation of the illumination and reflectance components, is proposed. The dynamic range of the input image is controlled by applying a suitable non-linear function to the illumination, while the details are enhanced by processing the reflectance. An innovative spatially recursive rational filter is used to estimate the illumination. Moreover, to improve the visual quality results of two-branch Retinex operators when applied to videos, a novel three-branch technique is proposed which exploits both spatial and temporal filtering. Real-time implementation is obtained by designing an Application Specific Instruction-set Processor (ASIP). Optimizations are addressed at algorithmic and architectural levels. The former involves arithmetic accuracy definition and linearization of non-linear operators; the latter includes customized instruction set, dedicated memory structure, adapted pipeline, bypasses, custom address generator, and special looping structures. The ASIP is synthesized in standard-cells CMOS technology and its performances are compared to known Digital signal processor (DSP) implementations of real-time Retinex filters. As a result of the comparison, the proposed algorithmic/architectural design outperforms state-of-art Retinex-like operators achieving the best trade-off between power consumption, flexibility, and visual quality.
Giovanni RamponiEmail:

Sergio Saponara   is a Research Scientist and Assistant Professor at the University of Pisa. He was born in Bari, Italy, in 1975. He received the Electronic Engineering degree cum laude and the Ph.D. in Information Engineering, both from Pisa University, in 1999 and 2003, respectively. Since 2001 he collaborates with Consorzio Pisa Ricerche, Italy and in 2002 he was with IMEC, Belgium as Marie Curie research fellow. His research and teaching interests include electronic circuits and systems for multimedia, telecom and automation. He co-authored more than 40 papers including journals, conferences and patents. Luca Fanucci   is Associate Professor of Microelectronics at the University of Pisa. He was born in Montecatini, Italy, in 1965. He received the Doctor Engineer degree and the Ph.D. in Electronic Engineering from the University of Pisa in 1992 and 1996, respectively. From 1992 to 1996, he was with the European Space Agency's Research and Technology Center, Noordwijk, The Netherlands, and from 1996 to 2004 he was a Research Scientist of the Italian National Research Council in Pisa. His research interests include design technologies for integrated circuits and systems, with emphasis on system-level design, hardware/software co-design and low-power. He co-authored more than 100 journal/conference papers and holds more than 10 patents. Stefano Marsi   was born in Trieste, Italy, in 1963. He received the Doctor Engineer degree in Electronic Engineering (summa cum laude) in 1990 and the Ph.D. degree in 1994. Since 1995 he has held the position of researcher in the Department of Electronics at the University of Trieste where he is the teacher of courses in electronic field. His research interests include non-linear operators for image and video processing and their realization through application specific electronics circuits. He is author or co-author of more than 40 papers in international journals, proceedings of international conferences or contributions in books. Giovanni Ramponi   is Professor of Electronics at the Department of Electronics of the University of Trieste, Italy. His research interests include nonlinear digital signal processing, and the enhancement and feature extraction in images and image sequences. Prof. Ramponi has been an Associate Editor of the IEEE Signal Processing Letters and of the IEEE Transactions on Image Processing; presently is an AE of the SPIE Journal of Electronic Imaging. He has participated in various EU and National Research Projects. He is the co-inventor of various pending international patents and has published more than 140 papers in international journals and conference proceedings, and as book chapters. Prof. Ramponi contributes to several undergraduate and graduate courses on digital signal processing.   相似文献   
68.
A novel technique for the quantification of the iron content of copper precipitates in ferritic steels is presented. Energy-filtered (EF) imaging has been used to extract elemental maps with high spatial resolution. These maps contain enough information to attempt the quantification of the signal produced by the precipitates when either a line profile is measured across them or the whole image signal is integrated. Assumptions such as sphericity of the precipitates and composition variations are discussed. Special attention to the assessment of drift on the information extracted from EF images has been taken. Minimum detectability and optimum acquisition conditions are discussed.  相似文献   
69.
Integrated Aquifers Management (IAM) demands innovative tools and methods that are able to consider as much perspectives as possible. This research is aimed to design, apply and provide an indicator named Social Sustainable Aquifer Yield (SSAY), expressed in units of time that includes pure hydrological variables as well as social ones. The indicator is defined as the relation between the Residence Time, which is the relation between aquifer Storage (S) and Recharge (R) (S/R), and the relation between the aquifer Pumping (P) and the new variable named Aquifer Social Yield (ASY). The whole indicator is defined by this formula: (S/R)/(P/ASY). The assessment of the residence time is essential in aquifers with at least one of the following features: i) high hydraulic diffusivity, and ii) small volume of reserves. Finally, the variable ASY is defined as the average perception from the stakeholders about the maximum acceptable aquifer exploitation. This indicator has been successfully applied in the aquifers located in southern Jaen province (South Spain) belonging to the Water System SE4-Jaén Water Supply. The results probe the high utility of the indicator, especially in regards to the public participation processes.  相似文献   
70.
Self-organising neural models have the ability to provide a good representation of the input space. In particular the Growing Neural Gas (GNG) is a suitable model because of its flexibility, rapid adaptation and excellent quality of representation. However, this type of learning is time-consuming, especially for high-dimensional input data. Since real applications often work under time constraints, it is necessary to adapt the learning process in order to complete it in a predefined time. This paper proposes a Graphics Processing Unit (GPU) parallel implementation of the GNG with Compute Unified Device Architecture (CUDA). In contrast to existing algorithms, the proposed GPU implementation allows the acceleration of the learning process keeping a good quality of representation. Comparative experiments using iterative, parallel and hybrid implementations are carried out to demonstrate the effectiveness of CUDA implementation. The results show that GNG learning with the proposed implementation achieves a speed-up of 6×6× compared with the single-threaded CPU implementation. GPU implementation has also been applied to a real application with time constraints: acceleration of 3D scene reconstruction for egomotion, in order to validate the proposal.  相似文献   
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