Synthesis of Millimeter‐Scale Transition Metal Dichalcogenides Single Crystals

The emergence of semiconducting transition metal dichalcogenide (TMD) atomic layers has opened up unprecedented opportunities in atomically thin electronics. Yet the scalable growth of TMD layers with large grain sizes and uniformity has remained very challenging. Here is reported a simple, scalable chemical vapor deposition approach for the growth of MoSe₂ layers is reported, in which the nucleation density can be reduced from 10⁵ to 25 nuclei cm^?2, leading to millimeter‐scale MoSe₂ single crystals as well as continuous macrocrystalline films with millimeter size grains. The selective growth of monolayers and multilayered MoSe₂ films with well‐defined stacking orientation can also be controlled via tuning the growth temperature. In addition, periodic defects, such as nanoscale triangular holes, can be engineered into these layers by controlling the growth conditions. The low density of grain boundaries in the films results in high average mobilities, around ≈42 cm² V^?1 s^?1, for back‐gated MoSe₂ transistors. This generic synthesis approach is also demonstrated for other TMD layers such as millimeter‐scale WSe₂ single crystals.     

Low-rate turbo-Hadamard codes

This paper is concerned with a class of low-rate codes constructed from Hadamard code arrays. A recursive encoding principle is employed to introduce an interleaving gain. Very simple trellis codes with only two or four states are sufficient for this purpose, and the decoding cost involved in the trellis part is typically negligible. Both simulation and analytical results are provided to demonstrate the advantages of the proposed scheme. The proposed scheme is of theoretical interest as it can achieve performance of BER=10/sup -5/ at E/sub b//N/sub 0//spl ap/-1.2dB (only about 0.4 dB away from the ultimate low-rate Shannon limit) with an information block size of 65534. To the authors' knowledge, this is the best result achieved to date with respect to the ultimate Shannon limit. With regard to practical issues, the decoding complexity of the proposed code is considerably lower than that of existing low-rate turbo-type codes with comparable performance.     

Built-in redundancy analysis for memory yield improvement

With the advance of VLSI technology, the capacity and density of memories is rapidly growing. The yield improvement and testing issues have become the most critical challenges for memory manufacturing. Conventionally, redundancies are applied so that the faulty cells can be repairable. Redundancy analysis using external memory testers is becoming inefficient as the chip density continues to grow, especially for the system chip with large embedded memories. This paper presents three redundancy analysis algorithms which can be implemented on-chip. Among them, two are based on the local-bitmap idea: the local repair-most approach is efficient for a general spare architecture, and the local optimization approach has the best repair rate. The essential spare pivoting technique is proposed to reduce the control complexity. Furthermore, a simulator has been developed for evaluating the repair efficiency of different algorithms. It is also used for determining certain important parameters in redundancy design. The redundancy analysis circuit can easily be integrated with the built-in self-test circuit.     

Selectively breaking data dependences to improve the utilization of idle cycles in algorithm level re-computing data paths

Although algorithm level re-computing techniques can trade-off the fault detection capability vs. time overhead of a Concurrent Error Detection (CED) scheme, they result in 100% time overhead when the strongest CED capability is achieved. Using the idle cycles in the data path to do the re-computation can reduce this time overhead. However, dependences between operations prevent the re-computation from fully utilizing the idle cycles. Deliberately breaking some of these data dependences can further reduce the time overhead associated with algorithm level re-computing. According to the experimental results the proposed technique, it brings time overhead down to 0-60% while the associated hardware overhead is from 12% to 50% depending on the design size.     

Solder joint reliability of TFBGA assemblies with fresh and reworked solder balls

In this article, the solder joint reliability of thin and fine-pitch BGA (TFBGA) with fresh and reworked solder balls is investigated. Both package and board level reliability tests are conducted to compare the solder joint performance of test vehicle with fresh and reworked solder balls. For package level reliability test, ball shear test is performed to evaluate the joint strength of fresh and reworked solder balls. The results show that solder balls with rework process exhibit higher shear strength than the ones without any rework process. The results also exhibit that the different intermetallic compound (IMC) formation at solder joints of fresh and reworked solder balls is the key to degradation of shear strength. For board level reliability tests, temperature cycling and bending cyclic tests are both applied to investigate the fatigue life of solder joint with fresh and reworked solder balls. It is observed that package with reworked solder ball has better fatigue life than the one with fresh solder ball after temperature cyclic test. As for bending cyclic test, in addition to test on as-assembled packages, reworked and fresh samples are subjected to heat treatment at 150 °C for 100 h prior to the bending cyclic test. The purpose is to let Au–Ni–Sn IMC resettle at solder joints of fresh solder ball and examine the influence of Au–Ni–Sn IMC on the fatigue life of solder joints (Au embrittlement effect). The final results confirm that reworked solder balls have better reliability performance than fresh one since Au embrittlement dose exist at fresh solder ball.     

低应力PECVD SiC晶圆级薄膜封装新技术

为了解决MEMS封装过程中易对微致动件造成损伤的问题,提出了一种低成本、与CMOS工艺兼容的晶圆级薄膜封装技术,用等离子体增强化学气相淀积(PECVD)法制备的低应力SiC作为封装和密封材料。此材料的杨氏模量为460 GPa,残余应力为65 MPa,可使MEMS器件悬浮时封装部位不变形。与GaAs,Si半导体材料相比,SiC具有较佳的物理稳定性,较高的杨氏模量等性能优势。将PECVD薄膜封装技术用于表面微结构和绝缘膜上Si(SOI)微结构部件(如射频开关、微加速度计等)封装中,不仅减小了封装尺寸,降低了芯片厚度,简化了封装工艺,而且封装芯片还与CMOS工艺兼容。较之晶圆键合封装方式,此晶圆级薄膜封装成本可降低5%左右。     

GaAs/Al_xGa_(1-x)As量子阱红外探测器光谱特性的研究

采用MBE法制备了不同结构参数及不同阱中掺杂浓度的GaAs/AlxGa1-xAs量子阱红外探测器外延材料。通过对量子阱红外探测器材料特性和器件特性的实验测试及理论分析,研究了量子阱红外探测器的响应光谱特性,并通过薛定谔方程和泊松方程的求解,对掺杂对量子阱能级的影响做了研究。结果表明,由于应力导致的能带非抛物线性使得阱中能级发生了变化,从而引起吸收峰向高能方向发生了漂移,而阱中进行适度的掺杂没有对量子阱能级造成影响,光致发光谱实验结果与之吻合较好。在光电流谱的实验分析基础之上,分析了量子阱阱宽、Al组分与峰值探测波长λ的关系,为量子阱红外探测器的设计优化提供了参考。     

低温漂高PSRR新型带隙基准电压源的研制

利用带隙电压基准的基本原理,结合自偏置共源共栅电流镜以及适当的启动电路,设计了一种新型基准电压源。获得了一个低温度系数、高电源抑制比的电压基准。通过对输出端添加运算放大器,把带隙基准电路产生的1.2 V电压提高到3.5 V,提高了芯片性能。用Cadence软件和CSMC的0.5μm CMOS工艺进行了仿真,结果表明,当温度在-20～+120℃,温度系数为9.3×10-6/℃,直流时的电源抑制比为-82 dB。该基准电压源能够满足开关电源管理芯片的使用要求,并取得了较好的效果。     

阵列位相环匀光器

基于衍射光学中的角谱理论,针对一种分布为同心3环、相位为0.9π,0和0.9π的结构进行深入分析,提出一种10×10的3环2值位相环阵列结构,并与二元光学中的10×10的菲涅尔波带片阵列结构进行比较,应用MATLAB软件仿真632.8nm激光器的高斯光通过二者后的效果。结果表明,阵列3环2值位相环对高斯光的匀光效果要明显优于阵列菲涅尔波带片,该阵列可以对激光束在远场的衍射光场进行修正,能较大地改善高斯光的匀光效果,在光均匀性要求较高的场合具有广泛的应用前景。     

绒面掺铝氧化锌透明导电薄膜研究进展

绒面掺铝氧化锌(AZO)透明导电薄膜由于电阻率低、在可见光区域透过率高、绒面结构能有效散射入射光,提高太阳电池光电转换效率,被广泛应用于太阳电池前电极。概述了绒面AZO薄膜的制备方法,重点介绍了磁控溅射技术沉积AZO薄膜后再进行湿法刻蚀制绒面方法,制备的样品呈现"坑状"或"类月球地貌"的绒面,并讨论了工艺对薄膜结构、光电性能和刻蚀行为的影响,最后介绍了绒面AZO薄膜在硅薄膜太阳电池中的应用,进一步降低生产成本和实现大规模产业化生产是绒面AZO薄膜的发展趋势。