边缘检测算子在汽车牌照区域检测中的应用

本文介绍了常用的几种边缘检测算子,不同的微分算子对不同边缘检测的敏感程度是不同的,因此对不同类型的边缘提取,应该采用对此类边缘敏感的算子进行边缘提取.针对车辆牌照自动识别,通过Matlab6.5进行了仿真研究,并比较和分析了这些算子的特点和作用,从中选出了合适的方法.     

基于因特网的监控录像系统的实现

介绍了一种基于因特网的监控录像系统,详细介绍了本系统的建模和软硬件模型,并阐述了本系统的软硬件实现方法。     

A common-gate switched 0.9-W class-E power amplifier with 41% PAEin 0.25-μm CMOS

A power amplifier for wireless applications has been implemented in a standard 0.25-μm CMOS technology. The power amplifier employs class-E topology to exploit its soft-switching property for high efficiency. The finite dc-feed inductance in the class-E load network allows the load resistance to be larger for the same output power and supply voltage than that for an RF choke. The common-gate switching scheme increases the maximum allowable supply voltage by almost twice from the value for a simple switching scheme. By employing these design techniques, the power amplifier can deliver 0.9-W output power to 50-Ω load at 900 MHz with 41% power-added efficiency (PAE) from a 1.8-V supply without stressing the active devices     

Energy Exchanged Process of Superradiant Optically Pumped Far-Infrared Laser with Buffer Gas

By means of solving the density matrix equations, base on the mechanism model of buffer gas, the output intensity of FIR and the FIR signal gain coefficient Gs and IR pumping signal absorption coefficient Gp were calculated, energy exchanged process of superradiant OPFIRL with buffer gas was analyzed. It was found that after adding buffer gas into the laser medium, the FIR output could be increased, and the active region of a FIR laser was lengthened.     

Performance evaluation of LIBTA/hybrid time‐slot selection algorithm for cellular systems

This paper studies the performance of radio assignment algorithms for portable access in cellular systems. Several channel access procedures are proposed and simulated using block oriented network simulator (BONeS) simulation of a model 36‐port system. Simulation results exhibit that load‐sharing system with LIBTA algorithm is better than directed retry system with the same algorithm by around 0.9 erlangs while better than quasi‐fixed channel assignment (QFCA) system by around 2 erlangs if the grade of service (GOS) is constrained to less than 10 per cent. Plus, a hybrid time‐slot selection procedure is proposed to enhance the system performance. It is observed that systems with hybrid time‐slot selection perform better than those with LIBTA algorithm in GOS under heavy load. It is also observed that load sharing system with hybrid time‐slot selection algorithm is better than directed retry system with the same algorithm by around 0.7 erlangs and better than QFCA system by around 2 erlangs. Copyright © 2001 John Wiley & Sons, Ltd.     

Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems

In this paper, a novel reconfigurable discrete wavelet transform processor architecture is proposed to meet the diverse computing requirements of future generation multimedia SoC. The proposed architecture mainly consists of reconfigurable processing element array and reconfigurable address generator, featuring dynamically reconfigurable capability where the wavelet filters and wavelet decomposition structures can be reconfigured as desired at run-time. The lifting-based reconfigurable processing element array possesses better computation efficiency than convolution-based architectures, and a systematic design method is provided to generate the hardware configurations of different wavelet filters for it. The reconfigurable address generator handles flexible address generation for data I/O access in different wavelet decomposition structures. A prototyping chip has been fabricated by TSMC 0.35 μm 1P4M CMOS process. At 50 MHz, this chip can achieve at most 100 M pixels/sec transform throughput, together with energy efficiency and unique reconfigurability features, proving it to be a universal and extremely flexible computing engine for heterogeneous reconfigurable multimedia systems.Po-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems.Chao-Tsung Huang was born in Kaohsiung, Taiwan, R.O.C., in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 2001. He currently is working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for signal processing systems.Liang-Gee Chen (S’84–M’86–SM’94–F’01) received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively. In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of VLSI Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

Model of Transforming Trajectory Coordinates of Trajectory Correction Projectile Measured by Ship Borne Tracking Radar

弹道修正弹是目前信息化弹药的研究热点之一,为了对舰炮发射修正弹后的实际弹道与预定弹道进行比较、形成修正指令,建立了舰载雷达所测量的相对弹道到相对地球静止的绝对坐标系的转换模型,解决了舰炮发射修正弹以后舰艇继续航行,雷达随舰艇运动、摇摆和升沉对测量弹道的影响.仿真结果证明,该模型是可行的,可为进一步研究弹道辨识问题提供依据.     

WCDMA室内分布系统设计相关问题探讨

结合WCDMA现网测试,对室内分布系统存在的干扰问题进行了研究,讨论并分析了室内分布系统的布放设计方案,提出了对室内分布系统设计有一定参考价值的建议     

Differential bidirectional transceiver for on-chip long wires

This work presents a differential bidirectional transceiver (DBT) for on-chip long wires. To enhance operating speed and reduce power consumption, the voltage swing on the wire is reduced using current-mode scheme. Consequently, our design performs higher data rate when wire length is extended. Moreover, adoption of differential scheme with a moderate tradeoff of area effectively lowers power supply noise and common mode noise. The receiver adopts four input differential pairs along with current summation circuit to evaluate small signal differences of every that state resulted from transmitting different data. Simulations using 0.18-μm device model indicates that the total input to output delay over a 5 mm long wire is 0.96 ns, with a power consumption of 8.724 mW at a speed of 1.2 Gbps and a maximum achievable data rate of 1.5 Gbps. A test chip is realized and successfully verifies the performance of the transceiver.     

杨木爆破浆作新闻纸配浆的初步研究

进行了杨木爆破浆配抄新闻纸的研究，杨木爆破浆取代马尾松化学浆配抄新闻纸后除撕裂度略有下降外，裂断长、拉毛速度、印刷密度、透印值等都有明显改善