High Temperature Superconducting Magnetic Energy Storage and Its Power Control Technology

High temperature superconducting （HTS） power inductor and its control technology have been studied and analyzed in the paper. Based on the results of simulations and practical experiments, a controlled release scheme has been proposed and verified for developing a practical HTS SMES prototype.     

Multicast deflector

Technological evolution is leading telecommunications toward all-IP scenarios, where multiple services are transported as IP packets. Among these services is the broadcast of video. A possible mechanism for broadcasting multiple video channels over IP is to use IP multicast, and let each client decide about the reception of a channel. The secure IP multicast specified by the IETF MSEC working group is a candidate solution for securing these broadcast services. In this paper we propose a new solution for supporting the broadcast of multiple video channels which can be accessed only by authorized users; besides, when a video channel is not visualized in the last mile its transmission is temporarily suspended, so that the cable can be used for other services such as standard Internet access.     

A Low-Latency Multi-layer Prefix Grouping Technique for Parallel Huffman Decoding of Multimedia Standards

Huffman coding is a popular and important lossless compression scheme for various multimedia applications. This paper presents a low-latency parallel Huffman decoding technique with efficient memory usage for multimedia standards. First, the multi-layer prefix grouping technique is proposed for sub-group partition. It exploits the prefix characteristic in Huffman codewords to solve the problem of table size explosion. Second, a two-level table lookup approach is introduced which can promptly branch to the correct sub-group by level-1 table lookup and decode the symbols by level-2 table lookup. Third, two optimization approaches are developed; one is to reduce the branch cycles and the other is parallel processing between two-level table lookup and direct table lookup approaches to fully utilize the advantage of VLIW parallel processing. An AAC Huffman decoding example is realized on the Parallel Architecture Core DSP (PAC DSP) processor. The simulation results show that the proposed method can further improve about 89% of decoding cycles and 33% of table size comparing to the linear search method.

A PVT Tolerant 10 to 500 MHz All-Digital Phase-Locked Loop With Coupled TDC and DCO

An all-digital phase-locked loop (ADPLL) with all components working with time interval or period signals is demonstrated. The ADPLL consists mainly of a free-running ring oscillator (FRO), a time to digital converter (TDC), a digitally controlled oscillator (DCO), a digital divider and a digital loop filter. In the proposed architecture, the TDC and DCO have an equal time resolution from the common FRO. The digital divider keeps the loop gain constant when the frequency multiplication factor changes. As a result, the ADPLL is inherently stable regardless of the variations of the process, supply voltage and temperature (PVT). The ADPLL is fabricated in 0.13 $mu$m CMOS process. Measurement results show that it works well over wide operation conditions, with the input frequencies ranging from 37.5 KHz to 25 MHz, frequency multiplication factors from 10 to 255, output frequencies from 10 MHz to 500 MHz, and supply voltages from 0.6 V to 1.6 V.      

Efficient design of anti-jamming rateless coding in cognitive OFDM

Efficient anti-jamming rateless coding based on cognitive Orthogonal Frequency Division Multiplexing (OFDM) modulation in Cognitive Radio Network (CRN) is mainly discussed. Rateless coding with small redundancy and low complexity is presented, and the optimal design methods of building rateless codes are also proposed. In CRN, anti-jamming rateless coding could recover the lost packets in parallel channels of cognitive OFDM, thus it protects Secondary Users (SUs) from the interference by Primary Users (PUs) efficiently. Frame Error Rate (FER) and throughput performance of SU employing anti-jamming rateless coding are analyzed in detail. Performance comparison between rateless coding and piecewise coding are also presented. It is shown that, anti-jamming rateless coding provides low FER and Word Error Rate (WER) performance with uniform sub-channel selection. Meanwhile, it is also verified that, in higher jamming rate and longer code redundancy scenario, rateless coding method could achieve better FER and throughput performance than another anti-jamming coding schemes.     

Comparative Study on the Properties of Galvanically Deposited Nano- and Microcrystalline Thin Films of PbSe

Thin films of PbSe having both nano- and microstructures have been deposited on transparent conducting oxide (TCO)-coated glass substrates electrochemically, from an aqueous solution of Pb(OAc)₂, ethylenediamine tetraacetic acid (EDTA), and SeO₂. A Pb strip acted as the sacrificial anode, while the TCO glass was the cathode. No external bias was applied. The formation of PbSe was pH sensitive, and pH ~3 was found to be optimum for film deposition. Films grown at room temperature (25°C) were nanocrystalline (~25 nm), while those deposited at 80°C were microcrystalline (~150 nm). Films were characterized by x-ray diffraction studies, field-emission scanning electron microscope image analysis, infrared spectral analysis, and by both alternating-current (a.c.) and direct-current (d.c.) electrical measurements. A blue-shift was observed for the nanocrystalline films. Film resistivity and junction properties were obtained from electrical measurements.     

用衍射谱表征颗粒形状

本文讨论了一种描述颗粒形状的新方法，给出了颗粒形状与颗粒衍射谱角分布的关系．     

A routing algorithm for reducing optical loss in photonic Networks-on-Chip

Driven by increase in automation, smart homes play an important role in today’s human life. This paper presents a new model for smart home technologies based on multi-device bidirectional visible light communication (VLC). For multiple devices and users, orthogonal code-based wavelength division (color beams) full-duplexed bidirectional VLC link is proposed. The color beams from RGB LEDs are utilized to transmit data and synchronize multi-device transmission. To enhance the performance of the proposed model, receiver diversity is also employed. Performance evaluation reveals that the proposed VLC-based model for smart homes is efficient with superior BER performance in a typical smart home environment except for the far corners. The maximum achievable data rate for each user up to four users is found to be 24 Mbps at both uplink and downlink transmissions.     

Resource efficiency improved approach for shared path protection in EONs

For improving the resource efficiency of dynamic shared path protection in elastic optical networks, a survivable RSA (SRSA)-based heuristic algorithm is proposed in the paper. In SRSA, an adaptive adjustment link cost function is devised to effectively select working and protection paths. The cost function sufficiently considers available spectrum resources and the length of light paths for both working and protection paths. In order to achieve high resource efficiency, a spectrum allocation strategy named minimal cost stable set is proposed to allocate spectrum for protection paths with respect to the resource efficiency in the link cost function. And the graph coloring algorithm is introduced to select the shared protection path with the highest resource efficiency for the request. Compared with the shared path protection and dynamic load balancing shared path protection, simulation results show that the proposed SRSA decreases bandwidth blocking probability and achieves high resource efficiency.     

Temperature compensated and gated CMOS ring oscillator for time-to-digital converter application

This paper presents a CMOS voltage controlled ring oscillator with temperature compensation for low power time-to-digital converters (TDCs). In order to maintain the oscillation frequency stable, a novel compensation circuit is proposed through adaptively sensing temperature variations. This design has been implemented in TSMC 0.35 μm CMOS standard process with an active area of under 0.039 mm². Experimental results show that the clock frequency is around 159.0 MHz only with a power consumption of 550 μA. As respective to the room temperature the maximum frequency variation is between ?3.46 and +3.08 % under temperature range of ?40 to 85 °C. The bit error time induced by clock jitter is limited within 4.8 % in the whole clock period, and the differential nonlinearity of the TDC is less than 0.408 LSB.