A comparative study of the kinetics of interfacial reaction between eutectic solders and Cu/Ni/Pd metallization

A comparative study of the kinetics of interfacial reaction between the eutectic solders (Sn-3.5Ag, Sn-57Bi, and Sn-38Pb) and electroplated Ni/Pd on Cu substrate (Cu/Ni/NiPd/Ni/Pd) was performed. The interfacial microstructure was characterized by imaging and energy dispersive x-ray analysis in scanning electron microscope (SEM). For a Pd-layer thickness of less than 75 nm, the presence or the absence of Pd-bearing intermetallic was found to be dependent on the reaction temperature. In the case of Sn-3.5Ag solder, we did not observe any Pd-bearing intermetallic after reaction even at 230°C. In the case of Sn-57Bi solder the PdSn₄ intermetallic was observed after reaction at 150°C and 180°C, while in the case of Sn-38Pb solder the PdSn₄ intermetallic was observed after reaction only at 200°C. The PdSn₄ grains were always dispersed in the bulk solder within about 10 μm from the solder/substrate interface. At higher reaction temperatures, there was no Pd-bearing intermetallic due to increased solubility in the liquid solder. The presence or absence of Pd-bearing intermetallic was correlated with the diffusion path in the calculated Pd-Sn-X (X=Ag, Bi, Pb) isothermal sections. In the presence of unconsumed Ni, only Ni₃Sn₄ intermetallic was observed at the solder-substrate interface by SEM. The presence of Ni₃Sn₄ intermetallic was consistent with the expected diffusion path based on the calculated Ni-Sn-X (X=Ag, Bi, Pb) isothermal sections. Selective etching of solders revealed that Ni₃Sn₄ had a faceted scallop morphology. Both the radial growth and the thickening kinetics of Ni₃Sn₄ intermetallic were studied. In the thickness regime of 0.14 μm to 1.2 μm, the growth kinetics always yielded a time exponent n >3 for liquid-state reaction. The temporal law for coarsening also yielded time exponent m >3. The apparent activation energies for thickening were: 16936J/mol for the Sn-3.5Ag solder, 17804 J/mol for the Sn-57Bi solder, and 25749 J/mol for the Sn-38Pb solder during liquid-state reaction. The corresponding activation energies for coarsening were very similar. However, an apparent activation energy of 37599 J/mol was obtained for the growth of Ni₃Sn₄ intermetallic layer during solid-state aging of the Sn-57Bi/substrate diffusion couples. The kinetic parameters associated with thickening and radial growth were discussed in terms of current theories.     

Interfacial reactions between a Pb-Free solder and die backside metallizations

The interfacial reactions between Sn-3.0 Ag-0.7 Cu solder and backside metallizations on two semiconductor devices, field-effect transistors (FET) and diode, are studied. The metallizations on both devices were vacuum evaporated Ti/Ni/Ag. The intermetallic compounds (IMC) formed near the diode/solder and FET/solder joints during reflow, and the interdiffusion processes during solid state aging are characterized by the quantitative energy dispersive x-ray analysis and the x-ray mapping technique in a scanning electron microscope. Two different intermetallic compounds are found near the diode/solder interface. Both are in the form of particles, not a continuous layer, and are referred to as IMC-I and IMC-II. IMC-I corresponds to Ni₃Sn₄, with Cu atoms residing on the Ni sublattice. It is uncertain whether IMC-II is Cu₆Sn₅ or a Cu-Ni-Sn ternary phase. Near the as-reflowed FET/solder interface, both isolated scallops and a skeleton-like layer of Ni₃Sn₄ are observed. The primary microstructural dynamics during solid-state aging are the coarsening of IMCs and the reactions involving the Ni-and Ti-layer with Sn and Au. While the reaction with the Ni-layer yields only Ni₃Sn₄ intermetallic, the reaction involving the Ti-layer suggests the formation of Ti-Sn and Au-Sn-Ti intermetallics. The latter is due to the diffusion of Au from the substrate side to the die side. It is postulated that the kinetics of the Au-Sn-Ti layer is primarily governed by the diffusion of Au through the Ni₃Sn₄ layer by a grain boundary mechanism.     

Midwavelength Infrared Avalanche Photodiode Using InAs–GaSb Strain Layer Superlattice

InAs-GaSb strain layer superlattice p⁺-n^--n avalanche photodiodes (APDs) are fabricated using a newly introduced electron-beam aided zinc sulfide deposition. Temperature-dependent measurements were performed on 300 times 300 mum² mesa etched APDs. The effect of passivation was also studied on the diode characteristics and APD performances. Temperature-dependent gain strongly correlates with avalanche mechanism.     

P-type double gate junctionless tunnel field effect transistor

We have investigated the 20 nm p-type double gate junctionless tunnel field effect transistor （P-DGJLTFET） and the impact of variation of different device parameters on the performance parameters of the P-DGJLTFET is discussed. We achieved excellent results of different performance parameters by taking the optimized device parameters of the P-DGJLTFET. Together with a high-k dielectric material （TiO2） of 20 nm gate length, the simulation results of the P-DGJLTFET show excellent characteristics with a high IoN of ～ 0.3 mA/μm, a low/OFF of ～ 30 fA/μm, a high ION/IOFF ratio of ～ 1×10^10, a subthreshold slope （SS） point of ～ 23 mV/decade, and an average SS of ～ 49 mV/decade at a supply voltage of -1 V and at room temperature, which indicates that PDGJLTFET is a promising candidate for sub-22 nm technology nodes in the implementation of integrated circuits.     

Parity generator and parity checker in the modified trinary number system using savart plate and spatial light modulator

The parity generators and the checkers are the most important circuits in communication systems. With the development of multi-valued logic (MVL), the proposed system with parity generators and checkers is the most required using the recently developed optoelectronic technology in the modified trinary number (MTN) system. This system also meets up the tremendous needs of speeds by exploiting the savart plates and spatial light modulators (SLM) in the optical tree architecture (OTA).     

Current-voltage characteristics of p-Si/carbon junctions fabricated by pulsed laser deposition

Amorphous carbon/p-Si junctions were fabricated at different temperatures using KrF excimer laser (λ = 248 nm, pulsed duration 20 ns). The current-voltage measurements of the devices showed diode characteristics. The value of various junction parameters such as ideality factor, barrier height, and series resistance were determined from forward bias I-V characteristics, Cheung method, and Norde’s function. There was a good agreement between the diodes parameters obtained from these methods. The ideality factor of ∼1.12 and barrier height of ∼0.37 eV were estimated using current-voltage characteristics for films grown at room temperature.     

A graph-theoretic approach for studying the convergence of fractalencoding algorithm

We present a graph-theoretic interpretation of convergence of fractal encoding based on partial iterated function system (PIFS). First we have considered a special circumstance, where no spatial contraction has been allowed in the encoding process. The concept leads to the development of a linear time fast decoding algorithm from the compressed image. This concept is extended for the general scheme of fractal compression allowing spatial contraction (on averaging) from larger domains to smaller ranges. A linear time fast decoding algorithm is also proposed in this situation, which produces a decoded image very close to the result obtained by an ordinary iterative decompression algorithm.     

Optimisation of electrical parameters in Fe DS-SBTFET and its application as a digital inverter

In this paper, the design geometry of Ferroelectric Dopant Segregated Schottky Barrier Tunnel Field Effect Transistor (Fe DS-SBTFET) has been proposed. Various electrical properties such as I_ON/I_OFF ratio and subthreshold swing (SS) of the proposed design have been premeditated and compared with different asymmetric structures. The impact of various types and thickness of buffer on the ferroelectric properties have been analysed. The device has been optimised for various doping concentrations and lengths of the dopant segregated layer (DSL). The digital applications of the proposed device in terms of complementary TFET digital inverter circuit have been studied. The transient characteristics and the delay parameters by considering various ferroelectric thicknesses have been analysed. Moreover, the transfer characteristics and electric field have been explored in the presence and absence of ferroelectric layer to obtain a better insight into the ferroelectric properties of the proposed structure. The electric field at the tunnelling junction is enhanced by the presence of ferroelectric layer which improves the ON current. The structure with ferroelectric thickness of 6 nm provides the best I_ON/I_OFF ratio of 1.2 × 10⁹ and SS of 14 mV/dec.     

Optimal Location of Energy Efficient DF Relay Node in $$\varvec{\kappa}$$ κ – $$\varvec{\mu }$$ μ Fading Channel

We investigate the optimal location of an adaptive decode and forward relay operating over a \(\kappa\)–\(\mu\) fading channel. The \(\kappa\)–\(\mu\) statistics provides a generalized line-of-sight propagation model which includes fading models like Rayleigh, Nakagami, Rician as special cases. We restrict our analysis to collinear relay placement, i.e. the relay node \((R_n)\) is on the same straight line between the source node \((S_n)\) and the destination node \((D_n)\). In the non-cooperative mode, \(D_n\) accepts only the two-hop transmission via \(R_n\) and discards any direct signal that may be available from \(S_n\). On the other hand, in the cooperative mode, \(D_n\) accepts both the replicas and combine them following either selection combining (SC) or maximum ratio combining (MRC). It is interesting to see that such cooperation does not always lead to energy saving, especially for small \(S_n-D_n\) separation. Also, worth mentioning the fact that MRC may not be optimal from the energy efficiency perspective, and SC can outperform MRC under certain channel conditions. In our paper, we also studied how parameters like spectral efficiency (R), path loss exponent (n), and fading parameters (\(\kappa ,\mu\)) affect the optimal relay placement location.