Distributed Multirobot Exploration and Mapping

Efficient exploration of unknown environments is a fundamental problem in mobile robotics. We present an approach to distributed multirobot mapping and exploration. Our system enables teams of robots to efficiently explore environments from different, unknown locations. In order to ensure consistency when combining their data into shared maps, the robots actively seek to verify their relative locations. Using shared maps, they coordinate their exploration strategies to maximize the efficiency of exploration. This system was evaluated under extremely realistic real-world conditions. An outside evaluation team found the system to be highly efficient and robust. The maps generated by our approach are consistently more accurate than those generated by manually measuring the locations and extensions of rooms and objects.     

Ultrathin Sticker‐Type ZnO Thin Film Transistors Formed by Transfer Printing via Topological Confinement of Water‐Soluble Sacrificial Polymer in Dimple Structure

To create ultrathin sticker‐type electronic devices that can be attached to unconventional substrates, it is highly desirable to develop printable membrane‐type electronics on a handling substrate and then transfer the printing to a target surface. A facile method is presented for high‐efficiency transfer printing by controlling the interfacial adhesion between a handling substrate and an ultrathin substrate in a systematic manner under mild conditions. A water‐soluble sacrificial polymer layer is employed on a dimpled handling substrate, which enables the topological confinement of the polymer residue inside and near the dimples during the etching and drying processes to reduce the interfacial adhesion gently, creating a high yield of transfer printing in a deterministic manner. As an example of an electronic device that was created using this method, a highly flexible sticker‐type ZnO thin film transistor was successfully developed with a thickness of 13 μm including a printable ultrathin substrate, which can be attached to various substrates, such as paper, plastic, and stickers.     

Decimal SRT Square Root: Algorithm and Architecture

Given the popularity of decimal arithmetic, hardware implementation of decimal operations has been a hot topic of research in recent decades. Besides the four basic operations, the square root can be implemented as an instruction directly in the hardware, which improves the performance of the decimal floating-point unit in the processors. Hardware implementation of decimal square rooters is usually done using either functional or digit-recurrence algorithms. Functional algorithms, entailing multiplication per iteration, seem inadequate to use for decimal square roots, given the high cost of decimal multipliers. On the other hand, digit-recurrence square root algorithms, particularly SRT (this method is named after its creators, Sweeney, Robertson, and Tocher) algorithms, are simple and well suited for decimal arithmetic. This paper, with the intention of reducing the latency of the decimal square root operation while maintaining a reasonable cost, proposes an SRT algorithm and the corresponding hardware architecture to compute the decimal square root. The proposed fixed-point square root design requires n+3 cycles to compute an n-digit root; the synthesis results show an area cost of about 31K NAND2 and a cycle time of 40 FO4. These results reveal the 14 % speed advantage of the proposed decimal square root architecture over the fastest previous work (which uses a functional algorithm) with about a quarter of the area.     

Performance analysis of OFDMA uplink systems with symbol timing misalignment

This letter presents our investigation for the effect of symbol timing errors in orthogonal frequency-division multiple access (OFDMA) uplink systems. We express the symbol timing errors between users as the symbol timing misalignments with respect to the desired user. Then, we derive an explicit expression of the signal-to-noise ratio (SNR) as a function of the maximum value of the symbol timing misalignments. Analyses and simulation results show that, to achieve an SNR of 20 dB, the maximum value of the symbol timing misalignments must be less than the cyclic prefix duration plus 6.25% of the useful symbol duration. Based on the resulting SNR degradation, we evaluate the SNR gain with guard subcarriers in order to mitigate the effect of the symbol timing misalignments.     

The design and the fabrication of monolithically integrated GaInAsP MQW laser with butt-coupled waveguide

We optimized the etching process for butt coupling to improve the reproducibility and the uniformity of the process for the integrated GaInAsP multiquantum-well laser with a butt-coupled waveguide. Three different ways of etching process were tested, which are reactive ion etching (RIE), RIE followed by a small amount (50 nm thick) of selective wet etching, and RIE followed by an adequate amount (125 nm thick) of selective wet etching. RIE followed by an adequate amount of selective wet etching showed the superior properties to the common expectation on RIE only, giving the measured coupling efficiency 96/spl plusmn/1.7% versus 34/spl plusmn/8%. The high coupling efficiency and the very small variation across a quarter of a 2-in wafer demonstrate that RIE coupled with an adequate amount of selective wet etching can also replace the conventional process for butt coupling, RIE followed by HBr-based nonselective wet etching, to fabricate high-quality integrated photonic devices.     

Design of Parasitic Inductance Reduction in GaN Cascode FET for High‐Efficiency Operation

This paper presents a method of parasitic inductance reduction for high‐speed switching and high‐efficiency operation of a cascode structure with a low‐voltage enhancement‐mode silicon (Si) metal–oxide–semiconductor field‐effect transistor (MOSFET) and a high‐voltage depletion‐mode gallium nitride (GaN) field‐effect transistor (FET). The method is proposed to add a bonding wire interconnected between the source electrode of the Si MOSFET and the gate electrode of the GaN FET in a conventional cascode structure package to reduce the most critical inductance, which provides the major switching loss for a high switching speed and high efficiency. From the measured results of the proposed and conventional GaN cascode FETs, the rising and falling times of the proposed GaN cascode FET were up to 3.4% and 8.0% faster than those of the conventional GaN cascode FET, respectively, under measurement conditions of 30 V and 5 A. During the rising and falling times, the energy losses of the proposed GaN cascode FET were up to 0.3% and 6.7% lower than those of the conventional GaN cascode FET, respectively.     

Efficient geocasting with multi-target regions in mobile multi-hop wireless networks

Geocasting, a variation on the notion of multicasting, is a mechanism to deliver messages of interest to all nodes within a certain geographical target region. Although several geocasting protocols have already been proposed for multi-hop wireless networks, most of these algorithms consider a “single” target region only. Here, when more than one target regions need to receive the same geocast messages, multiple transmissions need to be initiated separately by the message source. This causes significant performance degradation due to redundant packet transmissions, and it becomes more severe as the number of target regions increase. To solve this problem, we propose a basic scheme and its variations which utilize the geometric concept of “Fermat point” to determine the optimal junction point among multiple geocast regions from the source node. Our simulation study using ns-2 shows that the proposed schemes can effectively reduce the overhead of message delivery while maintaining a high delivery ratio in mobile multi-hop wireless networks.     

Intracranial Pressure Telemetry System Using Semicustom Integrated Circuits

A new generation of implantable, telemetric transmitters for intracranial pressure (ICP) measurements have been developed. A unique technique used in packaging the silicon piezoresistive pt essure transducer provides excellent long-term stability. Pulse code modulation is used for data transmission over a radio frequency (RF) link. To minimize the component count, two semicustom, bipolar integrated circuits are used. The transmitter electronics are housed inside a 29 ×20 ×7 mm titanium package along with the pressure transducer and two lithium batteries. Even though the transmitter consumes less than 0.4 mW of power, it is turned on remotely via RF signal transduction only on demand in order to extend the lifetime of the batteries to years. The pressure input of the transmitter has a dynamic range of ?100- +200 mmHg with a 0.3 mmHg resolution and a 1 mmHg accuracy. Long-term in vitro and in vivo pressure baseline stabilities of better than 1 and 2 mmHg per month, respectively, have been achieved.     

A Triode Device with a Gate Controllable Schottky Barrier: Germanium Nanowire Transistors and Their Applications

Electrical contacts often dominate charge transport properties at the nanoscale because of considerable differences in nanoelectronic device interfaces arising from unique geometric and electrostatic features. Transistors with a tunable Schottky barrier between the metal and semiconductor interface might simplify circuit design. Here, germanium nanowire (Ge NW) transistors with Cu₃Ge as source/drain contacts formed by both buffered oxide etching treatments and rapid thermal annealing are reported. The transistors based on this Cu₃Ge/Ge/Cu₃Ge heterostructure show ambipolar transistor behavior with a large on/off current ratio of more than 10⁵ and 10³ for the hole and electron regimes at room temperature, respectively. Investigations of temperature‐dependent transport properties and low‐frequency current fluctuations reveal that the tunable effective Schottky barriers of the Ge NW transistors accounted for the ambipolar behaviors. It is further shown that this ambipolarity can be used to realize binary‐signal and data‐storage functions, which greatly simplify circuit design compared with conventional technologies.