Bandwidth and region division for broadband multi-cell networks

A cell planning technique termed BRD (bandwidth and region division) is presented for overcoming interference, maintaining QoS (quality of service) and improving channel capacity over OFDM (orthogonal frequency division multiplexing)-based broadband cellular networks. Through an optimal combination of sectorization and zero padding, bandwidth and region division is achieved that minimizes the outage probability for forward-link cell planning. In order to verify the effectiveness of the proposed algorithm, a Monte Carlo simulation is performed over multi-cell environments.     

A practical approach for statistical matching of output queueing

We study a practical approach to match the performance of an output-queued switch statistically. For this purpose, we propose a novel switching architecture called a multiple input/output-queued (MIOQ) switch that requires no speedup for providing sufficient switching bandwidth. To operate an MIOQ switch in a practical manner, we also propose a multitoken-based arbiter which schedules the switch at a high operation rate and a virtual first-in first-out queueing scheme which guarantees the departure order of cells belonging to the same traffic flow at output. Additionally, we show that the proposed switch can naturally provide asymmetric bandwidth for inputs and outputs, which may be important in dealing with the links with different bandwidth demands. Finally, we compare the performance of an MIOQ switch with that of an output-queued switch and discuss the design criteria to match the performance of an output-queued switch.     

Data retention characteristics of sub-100 nm NAND flash memory cells

In contrast to the conventional theories, we have revealed that the most distinguished mechanism in the data retention phenomenon after Fowler-Nordheim (FN) stress in sub-100 nm NAND Flash memory cells is the annihilation of interface states. Interface state generation rate increases rapidly as the channel width of NAND flash cell decreases. Comparison of interface states and stress-induced leakage current (SILC) component during retention mode shows that the annihilation of interface states strongly affects data retention characteristics of the programmed cells.     

Orientation-based unique representation for planar curves and shapes

This paper presents an orientation-based representation for planar curves and shapes. The new representation can uniquely represent all types, of planar shapes, be it convex, nonconvex, polygonal, smoothly curved, or piecewise smooth shapes. It is based on a new parameterization, theabsolute integral orientation. This representation is invariant under translation and rotation. The absolute integral orientation is a parameter invariant under scaling. As a result, matching of similar shapes (i.e., determination of the relative orientation and the scaling factor) using the absolute integral orientation as the parameter is easier than using the arclength as the parameter. In addition, the new representation has the feature of adaptive sampling, making it more compact and efficient than arc-length-based representations.     

DC and AC characteristics of sub-50-nm MOSFETs with source/drain-to-gate nonoverlapped structure

A MOSFET structure with a nonoverlapped source/drain (S/D) to gate region was proposed to overcome the challenges in sub-50-nm CMOS devices. Key device characteristics were investigated by extensive simulation study. Fringing gate electric field through the spacer induces an inversion layer in the nonoverlap region to act as an extended S/D region. An oxide spacer is used to reduce parasitic gate overlap capacitance. A reasonable amount of inversion electrons were induced under the spacers. Internal physics, speed characteristics, short channel effects, and RF characteristics were studied with the nonoverlap distance at a fixed metallurgical channel length of 40 nm. The proposed structure had good drain-induced barrier lowering and V/sub T/ rolloff characteristics and showed reasonable intrinsic gate delay and cutoff frequency compared to those of an overlapped structure.     

89-GHz fT room-temperature silicon MOSFETs

The authors report the implementation of deep-submicrometer Si MOSFETs that at room temperature have a unity-current-gain cutoff frequency (f_T) of 89 GHz, for a drain-to-source bias of 1.5 V, a gate-to-source bias of 1 V, a gate oxide thickness of 40 Å, and a channel length of 0.15 μm. The fabrication procedure is mostly conventional, except for the e-beam defined gates. The speed performance is achieved through an intrinsic transit time of only 1.8 ps across the active device region     

A practical SPICE model based on the physics and characteristics of realistic single-electron transistors

A practical model for a single-electron transistor (SET) was developed based on the physical phenomena in realistic Si SETs, and implemented into a conventional circuit simulator. In the proposed model, the SET current calculated by the analytic model is combined with the parasitic MOSFET characteristics, which have been observed in many recently reported SETs formed on Si nanostructures. The SPICE simulation results were compared with the measured characteristics of the Si SETs. In terms of the bias, temperature, and size dependence of the realistic SET characteristics, an extensive comparison leads to good agreement within a reasonable level of accuracy. This result is noticeable in that a single set of model parameters was used, while considering divergent physical phenomena such as the parasitic MOSFET, the Coulomb oscillation phase shift, and the tunneling resistance modulated by the gate bias. When compared to the measured data, the accuracy of the voltage transfer characteristics of a single-electron inverter obtained from the SPICE simulation was within 15%. This new SPICE model can be applied to estimating the realistic performance of a CMOS/SET hybrid circuit or various SET logic architectures.