An Architecture of Scalable ATM Switching System and Its Call Processing Capacity Estimation

In this paper, we define the general requirements of ATM switching systems such as scalability, distributed fashion, and modularity. Also we propose a practical implementation of a scalable ATM switching system whose capacity can be easily expanded. Firstly, the architecture of the system is discussed with an emphasis on system scalability, modularity of subsystems and the simple control network of the design requirements. Secondly, we suggest the three types of distributed call/connection control schemes that are suitable for our switching system. We also estimate their call processing capacity on the average and make a comparison of them under the various system architectures. Since our scalable switching system can be constructed to perform the call processing functions on the various levels of the system capacity, it has much adaptability at the various evolution phases or regions of the network environment.     

Design and Architecture of Low‐Latency High‐Speed Turbo Decoders

In this paper, we propose and present implementation results of a high‐speed turbo decoding algorithm. The latency caused by (de)interleaving and iterative decoding in a conventional maximum a posteriori turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is from the combination of the radix‐4, center to top, parallel decoding, and early‐stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real‐time wireless communication services. The proposed scheme results in a slight degradation in bit error rate performance for large block sizes because the effective interleaver size in a radix‐4 implementation is reduced to half, relative to the conventional method. To prove the latency reduction, we implemented the proposed scheme on a field‐programmable gate array and compared its decoding speed with that of a conventional decoder. The results show an improvement of at least five fold for a single iteration of turbo decoding.     

High‐Performance Metal‐Substrate Power Module for Electrical Applications

This paper demonstrates the performance of a metal‐substrate power module with multiple fabricated chips for a high current electrical application, and evaluates the proposed module using a 1.5‐kW sinusoidal brushless direct current (BLDC) motor. Specifically, the power module has a hybrid structure employing a single‐layer heat‐sink extensible metal board (Al board). A fabricated motor driver IC and trench gate DMOSFET (TDMOSFET) are implemented on the Al board, and the proper heat‐sink size was designed under the operating conditions. The fabricated motor driver IC mainly operates as a speed controller under various load conditions, and as a multi‐phase gate driver using an N‐ch silicon MOSFET high‐side drive scheme. A fabricated power TDMOSFET is also included in the fabricated power module for three‐phase inverter operation. Using this proposed module, a BLDC motor is operated and evaluated under various pulse load tests, and our module is compared with a commercial MOSFET module in terms of the system efficiency and input current.     

The effects of bath composition on the morphologies of electroless nickel under-bump metallurgy on Al input/output pad

The electroless nickel plating on an aluminum input/output (I/O) pad was investigated. The aluminum pad was pretreated in a zincate solution prior to electroless nickel plating. Zinc particles on the aluminum pad gave a good adherent nickel layer. The adhesion and uniformity of zinc on the aluminum is the key factor in under-bump metallurgy (UBM). The electrode potential changes with and without zinc ions in the bath were measured to analyze the sequence of two competing reactions: zinc deposit and hydrogen evolution. The relationship between aluminum dissolution and the ratio of zinc and NaOH was investigated. The electroless nickel deposition rate was dependent on bath composition. The effects of complexing ligand and additive on the nickel deposit were analyzed. Electrode potential changes were measured with time to confirm nucleation and grain growth. Adhesion of the UBM was related to zinc-particle dissolution and nickel nucleation. The uniform nickel UBM was fabricated on a real Al I/O pad.     

The Design of Genetically Optimized Self-Organizing Neural Networks with Polynomial and Fuzzy Polynomial Neurons

In this study, we introduce and investigate a class of neural architectures of self-organizing neural networks (SONNs) that is based on a genetically optimized multilayer perceptron with polynomial neurons (PNs) or fuzzy polynomial neurons (FPNs), develop a comprehensive design methodology involving mechanisms of genetic optimization, and carry out a series of numeric experiments. We distinguish between two kinds of SONN architectures: (a) PN-based and (b) FPN-based SONNs. The augmented genetically optimized SONN (gSONN) results in a structurally optimized structure and comes with a higher level of flexibility in comparison to the one encountered in the conventional SONN. The genetic algorithm (GA)-based design procedure being applied at each layer of SONN leads to the selection of preferred nodes (PNs or FPNs) with specific local characteristics (such as the number of input variables, the order of the polynomial, and a collection of the specific subset of input variables) available within the network.     

A high-yield fabrication process for silicon neural probes

There is a great need for silicon microelectrodes that can simultaneously monitor the activity of many neurons in the brain. However, one of the existing processes for fabricating silicon microelectrodes-reactive-ion etching in combination with anisotropic KOH etching-breaks down at the wet-etching step for device release. Here we describe a modified wet-etching sidewall-protection technique for the high-yield fabrication of well-defined silicon probe structures, using a Teflon shield and low-pressure chemical vapor deposition (LPCVD) silicon nitride. In the proposed method, a micro-tab holds each individual probe to the central scaffold, allowing uniform anisotropic KOH etching. Using this approach, we obtained a well-defined probe structure without device loss during the wet-etching process. This simple method yielded more accurate fabrication and an improved mechanical profile.     

A dynamic ID management protocol for CSMA/IC in ad hoc networks

Contention based MAC protocols are widely used in ad hoc networks because they are suitable, where no central control node exists. However, contention based MAC protocols waste much time because of frequent collisions and long contention times. Moreover, it is hard for them to fairly distribute medium access opportunities. As a result, the problem of unfair medium access may arise under normal network conditions. Recently, another contention based MAC protocol, named the Carrier Sense Multiple Access/ID Countdown (CSMA/IC) was proposed. CSMA/IC resolves medium access contention by comparing the IDs of contending nodes with a simple signaling process. Therefore, medium access collisions never happen as long as each node possesses a unique ID, and the time cost for contention may be smaller than any other contention based MAC protocols if the number of IDs is managed so as to be as small as possible. Furthermore, CSMA/IC may support fair medium access by manipulating the ID of each node properly. In this paper, we propose a novel dynamic ID management protocol which enables a node to acquire a unique ID without any message exchanges and fairly distributed the number of medium access opportunities to all contending nodes. The proposed protocol also makes the contention process of CSMA/IC efficient by dynamically managing the length of the ID field according to the network traffic. The simulation results show that the proposed ID management protocol significantly improves the aforementioned aspects of CSMA/IC MAC protocol compared to previous ID management schemes.     

A 20-Gb/s 0.13-/spl mu/m CMOS serial link transmitter using an LC-PLL to directly drive the output multiplexer

A 20-Gb/s transmitter is implemented in 0.13-/spl mu/m CMOS technology. An on-die 10-GHz LC oscillator phase-locked loop (PLL) creates two sinusoidal 10-GHz complementary clock phases as well as eight 2.5-GHz interleaved feedback divider clock phases. After a 2/sup 20/-1 pseudorandom bit sequence generator (PRBS) creates eight 2.5-Gb/s data streams, the eight 2.5-GHz interleaved clocks 4:1 multiplex the eight 2.5-Gb/s data streams to two 10-Gb/s data streams. 10-GHz analog sample-and-hold circuits retime the two 10-Gb/s data streams to be in phase with the 10-GHz complementary clocks. Two-tap equalization of the 10-Gb/s data streams compensate for bandwidth rolloff of the 10-Gb/s data outputs at the 10-GHz analog latches. A final 20-Gb/s 2:1 output multiplexer, clocked by the complementary 10-GHz clock phases, creates 20-Gb/s data from the two retimed 10-Gb/s data streams. The LC-VCO is integrated with the output multiplexer and analog latches, resonating the load and eliminating the need for clock buffers, reducing power supply induced jitter and static phase mismatch. Power, active die area, and jitter (rms/pk-pk) are 165 mW, 650 /spl mu/m/spl times/350 /spl mu/m, and 2.37 ps/15 ps, respectively.     

Growth of tin whiskers for lead-free plated leadframe packages in high humid environments and during thermal cycling

Growth behavior of tin whiskers from pure tin and tin–bismuth plated leadframe (LF) packages for elevated temperature and high humidity storages and during thermal cycling was observed. In the storage at 60 °C/93% relative humidity (RH) and 85 °C/85%RH the galvanic corrosion occurred at the outer lead toes and shoulders where the base LF material is exposed, forming tin oxide layers of SnO₂. The corroded layers spread inside the film and formed whiskers around the corroded islands. Many whiskers were observed to grow from grain boundaries for the Fe–42Ni alloy (alloy42) LF packages. It was confirmed that the corrosion tends to occur on the side surfaces of outer leads adjacent to the mold flash. The contribution of ionic contaminants in epoxy mold compound (EMC) to the corrosion was not identified. During thermal cycling between −65 °C and +150 °C whiskers grew out of as-deposited grains for pure tin-plated alloy42 LF packages and they grew linearly with an increase of number of cycle. Growth mechanisms of the whiskers from grain boundaries and as-deposited grains were discussed from the deformation mechanism map for tin and mathematical calculation with a steady-state diffusion model.     

Statistical Characterization of Open Failures in the Fine-Pitch COG Interconnection

Chip-on-glass (COG) interconnection using anisotropic conductive film (ACF) is susceptible to open failures. Open failures can be induced by the absence of conductive particles or an insufficient contact. Experimental results as well as statistical approaches were used to understand the conditions for open failures in COG bonding. The binomial distribution was used to predict the probability of the open failure due to the deficiency of conductive particles. The probability of an open failure decreased with increasing bump area and decreasing particle size. The bump height variation was also an important factor that affected the probability of the open failure together with the bump-to-electrode gap and the particle size. The variation in bump height should be minimized to avoid open failures in fine-pitch applications where a smaller particle size is required.