A call to arms for task parallelism in multi‐scale materials modeling

Simulations based on multi‐scale material models enabled by adaptive sampling have demonstrated speedup factors exceeding an order of magnitude. The use of these methods in parallel computing is hampered by dynamic load imbalance, with load imbalance measurably reducing the achieved speedup. Here we discuss these issues in the context of task parallelism, showing results achieved to date and discussing possibilities for further improvement. In some cases, the task parallelism methods employed to date are able to restore much of the potential wall‐clock speedup. The specific application highlighted here focuses on the connection between microstructure and material performance using a polycrystal plasticity‐based multi‐scale method. However, the parallel load balancing issues are germane to a broad class of multi‐scale problems. Copyright © 2011 John Wiley & Sons, Ltd.     

The effect of pretinning on the solderability of copper

The reliability and integrity of pretinned, copper-clad printed circuit boards are serious concerns in the manufacture of electronic devices. The nature of wetting during the soldering of copper is critical in the reliability of these solder joints. Some preliminary experiments on the solderability of pretinned copper suggest that pretinning with a lead-rich solder, such as 95Pb-5Sn, is preferred to pretinning with a eutectic solder, because the latter can develop exposed intermetallics during aging or baking that wet poorly.     

Fast sequential least squares design of FIR filters with linearphase

The authors propose a fast adaptive least-squares algorithm for linear-phase finite-impulse-response (FIR) filters. The algorithm requires 10m multiplications per data point where m is the filter order. This reduced computation stems from the fast adaptive forward-backward least-squares method. Both linear-phase cases i.e. with constant phase delay and with constant group delay, are examined. Simulation results demonstrate that the proposed algorithm is superior to the least-mean-squares gradient algorithm and the averaging scheme used for the modified fast Kalman algorithm     

Analysis of low-temperature intermetallic growth in copper-tin diffusion couples

A multiphase diffusion model was constructed and used to analyze the growth of the ε- and η-phase intermetallic layers at a plane Cu-Sn interface in a semi-infinite diffusion couple. Experimental measurements of intermetallic layer growth were used to compute the interdiffusivities in theε andη phases and the positions of the interfaces as a function of time. The results suggest that interdiffusion in the ε phase(≈D _ε) is well fit by an Arrhenius expression with D₀ = 5.48 × 10⁻⁹ m²/s andQ = 61.9 kJ/mole, while that in the η phase (≈D_η) has D₀ = 1.84 × 10⁻⁹ m²/s andQ = 53.9 kJ/mole. These values are in reasonable numerical agreement with previous results. The higher interdiffusivity in theη phase has the consequence that theη phase predominates in the intermetallic bilayer. However, the lower activation energy for interdiffusion in theη phase has the result that theε phase fills an increasing fraction of the intermetallic layer at higher temperature: at 20 °C, the predicted ε-phase thickness is ≈10 pct of that ofη, while at 200 °C, its thickness is 66 pct of that ofη. In the absence of a strong Kirkendall effect, the original Cu-Sn interface is located within theη-phase layer after diffusion. It lies near the midpoint of theη-phase layer at higher temperature (220 °C) and, hence, appears to shift toward the Sn side of the couple. The results are compared to experimental observations on intermetallic growth at solder-Cu interfaces.     

Implementation of a Sliding Memory Plane Image Processor

This paper presents architectures and implementation of a Sliding Memory Plane (SliM) Image Processor to build a SIMD parallel computer. The paper also proposes an enhanced multiplication algorithm to reduce the gate count and the number of cycles. The SliM chip consists of mesh-connected 5×5 PEs. Due to the idea ofsliding, that is, overlapping the inter-PE communication time with the computation time, SliM can greatly reduce the inter-PE communication overhead. In addition, four operations corresponding to ALU, shift, data I/O, and inter-PE communication can be grouped into an instruction to be executed in a cycle simultaneously. The implemented SliM chip operates at 25 MHz and gives 625 MIPS. Because of a mesh topology, a large number of chips can be easily connected to form a SIMD parallel computer. We have implemented the scalable SliM Array Processor and developed parallel algorithms for real-time image processing.     

The effect of alkali promoters in oxidative coupling of methane with Mn-oxide catalysts

The catalytic oxidalive coupling of metnane to ethylene and ethane with manganese oxide catalysts promoted with alkali metal and alkali metallic-chloride has been studied at atmospheric pressure in a fixed bed flow reactor. The main studies of reaction were carried out over maganese oxide catalysts promoted with sodium chloride and the structure and surface morphology of these catalysts was characterized by an X-ray diffraction and a scanning electron microscope. The powdered MnO₂ was changed into Mn₂O₃, and MnO₂ containing alkali metallic-chlorides was not changed to new ternary oxides but changed into Mn₃O₄ and/or Mn₂O₃ at higher calcination temperature(above 780°C). The optimum content of NaCl promoted was 10–20wt%, an in over 10wt%, the conversion and the selectivity were kept constant. The main factor on deactivation of catalysts was the loss of thepromoter(NaCl). The addition of alkali metal salts to manganese oxide catalyst has enhanced C₂(C₂H₄ + C₂H₆) selectivity due to neutralizing acid sites more than the electronic factor. It was confirmed that chlorine in alkali metallicchloride has enhanced the formation of C₂H₄, resulting in a good C₂-yield (up to 25.7%).     

Automotive seat vibration control via hydraulic semiactive vibration absorbers (SAVA)

The paper examines the ride performance enhancement that can be obtained by applying hydraulic semiactive vibration absorbers (SAVA) to alter the compliance characteristics of the seat/wheel suspension system. The work relies on a consistent model of the (nonlinear) hydraulics of the SAVA. A recently developed Lyapunov control scheme is used for regulation. The performance is examined assuming a quarter car with a seat/seat mounted mass. The paper then employs a quarter car/seat with a two mass ISO model of the seated human. Two road conditions are employed in the simulations; a ride swell and a road surface with a white noise velocity profile. The results show 45% reduction of of the vertical acceleration.     

Implementation of a Wireless Multimedia DSP Chip for Mobile Applications

This paper presents the implementation of a wireless multimedia DSP chip for mobile applications. The implemented DSP chip supports communication instructions for Viterbi, timing synchronization, etc. as well as multimedia instructions. The DSP can handle variable length data and perform four MACs in a cycle. The proposed DSP employs parallel processing techniques, such as SIMD, vector processing, DSP schemes and adopts low power features for wireless applications. The implemented DSP chip includes test circuits and various peripherals, such as DMA, bus arbitration, timer, etc. This chip has been modeled by Verilog HDL and implemented using the 0.35 m HCB60 library. The total gate count excluding memory is about 170,000 gates and the clock frequency is 100 MHz.Junghoo Lee received the B.S. degree in electronic engineering from Ajou University, Suwon, Korea in 2002. He is currently working toward the Ph.D. degree with School of Electrical and Computer Engineering, Ajou University. His main research interests include SOC design and application-specific DSP chip design.Myung H. Sunwoo received the B.S. degree in electronic engineering from the Sogang University in 1980, the M.S. degree in electrical and electronics from the Korea Advanced Institute of Science and Technology in 1982, and the Ph.D. degree in electrical and computer engineering from the University of Texas at Austin in 1990.He worked for Electronics and Telecommunications Research Institute (ETRI) in Daejeon, Korea from 1982 to 1985 and Digital Signal Processor Operations, Motorola, Austin, TX from 1990 to 1992. Since 1992, he has been a Professor with the School of Electrical and Computer Engineering, Ajou University in Suwon, Korea. In 2000, he was a Visiting Professor in the Department of Electrical and Computer Engineering, the University of California, Davis, CA. He is the Director of the National Research Laboratory sponsored by the Ministry of Science and Technology. His research interests include VLSI architectures, SOC design for multimedia and communications, and application-specific DSP architectures.Dr. Sunwoo has published more than 120 papers in international transactions/journals and conferences and also has 28 patents including five U.S. patents. He served as a Technical Program Chair of the IEEE Workshop on Signal Processing Systems (SIPS) in 2003 and a member of the technical program committee of various international conferences. He has received a number of research awards from the Ministry of Commerce, Industry and Energy, Samsung Electronics, and professional foundations. He served as an Associate Editor for the IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2002–2003) and as a Guest Editor for the Journal of VLSI Signal Processing (Kluwer, 2004). Currently, He is a Senior Member of IEEE and a Chair of the IEEE CAS Society of the Seoul Chapter.