广钢转炉分厂2号方坯连铸机拉速问题的探讨

通过分析钢水在结晶器内凝固的不均匀性及对钢水结晶的热量平衡计算，讨论连铸中间包钢水温度、结晶器冷却水流量及进出水温差对拉坯速度的影响。     

Design and performance evaluation of a banyan network basedinterconnection structure for ATM switches

This paper presents a new self-routing packet network called the plane interconnected parallel network (PIPN). In the proposed design, the traffic arriving at the network is shaped and routed through two banyan network based interconnected planes. The interconnections between the planes distribute the incoming load more homogeneously over the network. The throughput of the network under uniform and heterogeneous traffic requirements is studied analytically and by simulation. The results are compared with the results of the baseline network and another banyan network based parallel interconnection network. It is shown that, for the proposed design, a higher degree of heterogeneity results in better performance     

Asymmetric dilation of multiwavelength cross-connect switches forlow-crosstalk WDM optical networks

We predict that, for wavelength division multiplexing optical-network applications, an asymmetrically dilated configuration of a 2×2 cross-connect is significantly better in terms of overall crosstalk when the levels of the bar-port crosstalk and the cross-port crosstalk are significantly different from each other, as is the case with optical-frequency filters which utilize grating-assisted coupling. As a verification, we present a simulation study with 2×2 polarization-diversified acousto-optic tunable filters. We present a recursive method to extend the principle of asymmetric dilation to larger-size cross-connect switches, and make a recommendation for an asymmetrically dilated 4×4 cross-connect configuration     

Optimal deterministic timeouts for reliable scalable multicast

Reliable multicast protocols suffer from the problem of feedback implosion. To avoid this problem, the number of receivers sending feedback in case of loss must be small. However, losses experienced by different receivers are strongly correlated, since receivers share common resources in the multicast tree. One approach to feedback implosion avoidance relies on delaying feedback at the receivers. We present deterministic timeouts for reliable multicast (DTRM), a distributed algorithm to compute optimal deterministic timeouts for each receiver in a multicast tree as a function of the tree topology and the sender-to-receiver round-trip delays. DTRM has several desirable properties. First, feedback implosion is provably avoided for a single loss anywhere in the tree, provided delay jitter is bounded. Second, the computation of the timeouts can be entirely distributed; receivers and intermediate nodes only rely on local topology information. Third, the timeouts computed by DTRM are optimal with respect to the maximum response time     

Finite element beam propagation method for three-dimensionaloptical waveguide structures

A beam propagation method (BPM) based on the finite element method (FEM) is described for longitudinally varying three-dimensional (3-D) optical waveguides. In order to avoid nonphysical reflections from the computational window edges, the transparent boundary condition is introduced. The present algorithm using the Pade approximation is, to our knowledge, the first wide-angle finite element beam propagation method for 3-D waveguide structures. To show the validity and usefulness of this approach, numerical results are shown for Gaussian-beam excitation of a straight rib waveguide and guided-mode propagation in a Y-branching rib waveguide     

Positive temperature dependence of the electron impact ionizationcoefficient in In0.53Ga0.47As/InP HBTs

Impact ionization is a major limiting factor to the maximum operating voltage of InGaAs-based, high-speed transistors. In this work, data on the positive temperature dependence of the electron impact ionization coefficient α_n in In_0.53Ga_0.47As at medium-low electric fields are reported for the first time. The increase of α_n with temperature is opposite to the behavior normally observed in most semiconductors. This anomalous behavior implies the onset of a positive feedback between power dissipation and avalanche generation which may adversely affect the power handling capability of In_0.53Ga _0.47As-based devices, and which should be taken into account in device thermal modeling. In the experimental procedure, based on the measurement of the multiplication factor M-1 in npn In_0.53Ga _0.47As/InP Heterojunction Bipolar Transistors (HBT), particular care has been taken in order to rule out possible spurious, temperature-dependent contributions to the measured multiplication current     

C-t analysis of MOS capacitors under constant current stress

The effect of high oxide field stress is studied using capacitance-time (C-t) measurements of MOS capacitors. The stress results in parallel shifts of the C-t curve along the time axis. The flatband voltage shift ΔV_FB obtained from the initial deep depletion capacitance C(t=0⁺) follows the same trend as that from the high-frequency C-V characteristics. However, the discrepancy between the two flatband voltages becomes larger as the stress increases due to the effect of interface charges on C-t characteristics. The flatband voltage difference is converted to interface trap density, showing a steady increase of interface trap density with stress, similar to that from low-frequency C-V measurements     

A fully soft-switched extended-period quasi-resonantpower-factor-correction circuit

This paper presents the design criteria, procedure, and implementation of a soft-switched power-factor-correction (PFC) circuit based on the extended-period quasi-resonant (EPQR) principles. All power electronic devices including switches and diodes in the circuit are fully soft switched. The design method is demonstrated in a prototype circuit. The operating principles are confirmed with computer simulation and experimental results. A comparison of the EP-QR operation and zero-voltage-transition (ZVT) pulse-width modulation (PWM) method     

Mixed Analog Digital Simulation of Integrated Circuits with BRASIL

In this paper the approach of BRASIL in modelling digitalintegrated circuits is presented. BRASIL consists of a timingsimulator for digital MOS circuits coupled with an algorithmfor circuit simulation. The timing simulation is based upon afast macromodelling approach and the calculation of time-variantRC networks. The circuit simulator takes advantage of structuringthe system of nodal equations. With BRASIL a fast and accuratesimulation of digital circuits, with special regard to the analogbehaviour of highly integrated systems is possible.