Over 1100 nm wavelength tuning in superstructure grating (SSG) DBR lasers

A broad range tuning of over 100 nm in tunable DBR lasers with superstructure grating (SSG) is reported. The SSG reflectors for 100 nm were designed and patterned by electron beam lithography. 1.55 mu m DBR lasers with SSG reflector operate in a single mode with a tuning range of 83 nm under CW conditions. With inclusion of the multimode operating region, the tuning range becomes as wide as 103 nm.<>     

A simple laterally tapered waveguide for low-loss coupling tosingle-mode fibers

Low-loss coupling between semiconductor photonic devices and single-mode fibers is achieved using a simple InP/InGaAsP tapered waveguide. The proposed simple structure has a small and nearly square guiding core at its output facet. In this structure, the output field has a non-Gaussian profile, but low-pass filter coupling can be achieved by optimizing the design of the guiding core sizes. The waveguide is composed of a laterally tapered InGaAsP guiding layer and an InP cladding region on an InP substrate, facilitating integration of the waveguide with active devices using conventional processes. The waveguide is shown to have a total insertion loss of 2.6 dB, including a coupling loss of 0.9 dB and large ±2.5-μm misalignment tolerance in lateral and vertical directions with single-mode filters     

A 320 MFLOPS CMOS floating-point processing unit for superscalarprocessors

A CMOS pipelined floating-point processing unit (FPU) for superscalar processors is described. It is fabricated using a 0.5 μm CMOS triple-metal-layer technology on a 61 mm² die. The FPU has two execution modes to meet precise scientific computations and real-time applications. It can start two FPU operations in each cycle, and this achieves a peak performance of 160 MFLOPS double or single precision with an 80 MHz clock. Furthermore, the original computation mode, twin single-precision computation, double the peak performance and delivers 320 MFLOPS single precision. Its full bypass reduces the latency of operations, including load and store, and achieves an effective throughput even in nonvectorizable computations. An out-of-order completion is provided by using a new exception prediction method and a pipeline stall technique     

An image analyzing system using an artificial neural network forevaluating the parenchymal echo pattern of cirrhotic liver and chronichepatitis

To objectively evaluate the parenchymal echo pattern of cirrhotic liver and chronic hepatitis, the authors applied an image analyzing system (IAS) using a neural network. Autopsy specimens in a water tank (n=13) were used to examine the relationship between the diameter of the regenerative nodule and the coarse score (CS) calculated by IAS. CS was significantly correlated with the diameter of the regenerative nodule (p<0.0001, r=0.966). CS is considered to be useful for evaluating the coarseness of the parenchymal echo pattern     

High-input-power saturation properties of apolarization-insensitive semiconductor Mach-Zehnder interferometer gateswitch for WDM applications

We propose that a polarization-insensitive Mach-Zehnder interferometer (MZI) switch is useful for optical gate elements, especially if multiwavelength signals are input. This device has high-input-power saturation properties, which shows that both the operating voltage and the extinction ratio do not change when the optical input power reaches at least +18 dBm. A high extinction ratio of 30 dB was achieved in the wide-wavelength range of 20 nm. Moreover, the extinction ratio can be improved by up to 45 dB by using a cascaded configuration to decrease crosstalk. These results indicate the MZI gate switch is well suited to wavelength-division multiplexing (WDM) network components     

Still image transmission using ARQ over Rayleigh fading channels

The authors propose a new ARQ scheme suitable for image transmission over radio channels. The proposed scheme detects only serious degradation and so attains higher throughput performance than the conventional ARQ scheme     

Dynamic voltage and frequency management for a low-power embedded microprocessor

High-performance and low-power microprocessors are key to PDA applications. A dynamic voltage and frequency management (DVFM) scheme with leakage power compensation effect is introduced in a microprocessor with 128-bit wideband 64-Mb embedded DRAM. The DVFM scheme autonomously controls clock frequency from 8 to 123 MHz in steps of 0.5 MHz and also adaptively controls supply voltage from 0.9 to 1.6 V in steps of 5 mV, achieving 82% power reduction in personal information management scheduler application and 40% power reduction in MPEG4 movie playback. This low-power embedded microprocessor, fabricated with 0.18-/spl mu/m CMOS embedded DRAM technology, enables high-performance operations such as audio and video applications. As process technology shrinks, this adaptive leakage power compensation scheme will become more important in realizing high-performance and low-power mobile consumer applications.     

High-bandwidth graded-index polymer optical fiber with high-temperature stability

A newly developed graded-index polymer optical fiber (GI-POF) with high-temperature and high-humidity stability was proposed. As it was found that the high numerical aperture and high glass transition temperature (T/sub g/) at the core center of the GI-POF were key issues to achieve both high-temperature and humidity stability, a partially fluorinated polymer material was adopted to obtain both characteristics in the GI-POF. The newly developed GI-POF had low-loss (140 dB/km at 650-nm wavelength), high-bandwidth (higher than 1 GHz for 100 m transmission), high-temperature and humidity stability at 70/spl deg/C, 80% relative humidity (R.H.) and low bending loss.     

适于运动估值VLSI实现的改进的树结构

文中给出了一种用于实现多分辨率运动估算算法后阶段任务的改进的树结构。在一个简单的RISC类型核控制下,它能够完成整个运动估值过程中除粗分辨率精度运动矢量搜索之外的所有后阶段子任务。包括运动矢量优化（搜索）在内的多任务是通过二叉树最底层叶节点上的多功能处理单元和可以拆分成子树的加法树来实现的。此外,运算单元寄存器堆的设计使能在二维方向上复用图像数据,完全避免了同一类数据从存储器中重复读取,从而实现了最小的存储器访问带宽,并有助于减小存储功耗。     

A real-time motion estimation and compensation LSI with wide searchrange for MPEG2 video encoding

This paper presents a motion estimation and compensation large scale integration (LSI) for the MPEG2 standard. An embedded RISC processor and special hardware modules enable the LSI to achieve a sufficient ability to perform real-time operation and provide the availability to realize many kinds of block matching algorithms. Using a three-step hierarchical telescopic search algorithm, a single chip accomplishes real-time motion estimation with search ranges of ±32.5×±32.5 pixels for motion vectors. The chip was fabricated using 0.5-μm CMOS technology and has an area of 16.5×16.5 mm² and 2.0 M transistors