济南市现代测绘基准体系建设

概述了济南市现代测绘基准体系建设背景和基本情况,详细介绍高精度GPS网、精密水准网、济南似大地水准面精化、JNCORS系统的建立、数据处理及测试等有关情况,分析了济南市现代测绘基准体系的创新点和应用前景。     

基于DS18B20的测温系统设计

针对传统温度检测装置存在的问题,提出了以AT89S51单片机和单总线数字温度传感器DS18820构成的新型温度测量系统。介绍DS18820的特性、内部结构以及单总线技术的特点。详细论述了该系统的设计方案、硬件组成及软件设计流程图。经测试,基于DS18820的测温系统具有结构简单、测温精度高、稳定可靠的优点。     

10 Gb/s OEIC optical receiver front-end and 3.125 Gb/s PHEMT limiting amplifier

A 10 Gb/s OEIC (optoelectronic integrated circuit) optical receiver front-end has been studied and fab ricated based on the φ-76 mm GaAs PHEMT process; this is the first time that a limiting amplifier (LA) has been designed and realized using depletion mode PHEMT. An OEIC optical receiver front-end mode composed of an MSM photodiode and a current mode transimpedance amplifier (TIA) has been established and optimized by simu lation software ATLAS. The photodiode has a bandwidth of 10 GHz, a capacitance of 3 fF/μm and a photosensitive area of 50×50 μm~2. The whole chip has an area of 1511×666 μm~2. The LA bandwidth is expanded by spiral inductance which has been simulated by software HFSS. The chip area is 1950×1910μm~2 and the measured results demonstrate an input dynamic range of 34 dB (10-500 mVpp) with constant output swing of 500 tnVpp.     

Influence of layout parameters on snapback characteristic for a gate-grounded NMOS device in 0.13-μm silicide CMOS technology

Gate-grounded NMOS （GGNMOS） devices with different device dimensions and layout floorplans have been designed and fabricated in 0.13-μm silicide CMOS technology. The snapback characteristics of these GGN-MOS devices are measured using the transmission line pulsing （TLP） measurement technique. The relationships between snapback parameters and layout parameters are shown and analyzed. A TCAD device simulator is used to explain these relationships. From these results, the circuit designer can predict the behavior of the GGNMOS devices under high ESD current stress, and design area-efficient ESD protection circuits to sustain the required ESD level. Optimized layout rules for ESD protection in 0.13-μm silicide CMOS technology are also presented.     

0.13微米硅化物 CMOS工艺下版图参数对栅极接地 NMOS晶体管骤回特性的影响

本文中,在 0.13微米硅化物 CMOS工艺下, 设计了不同版图尺寸和不同版图布局的栅极接地 NMOS器件。TLP测量技术用来获得器件的骤回特性。 文章分析了器件版图参数和器件骤回特性之间的关系。TCAD器件仿真软件被用来解释证明这些结论.通过这些结论,电路设计者可以预估栅极接地NMOS器件在ESD大电流情况下的特性,由此在有限的版图面积下设计符合 ESD保护要求的栅极接地 NMOS器件。本文同时给出了优化后的 0.13微米硅化物工艺下 ESD版图规则。     

Influence of layout parameters on snapback characteristic for a gate-grounded NMOS device in 0.13-μm silicide CMOS technology

r of the GGNMOS devices under high ESD current stress, and design area-efficient ESD protection circuits to sustain the required ESD level.Optimized layout rules for ESD protection in 0.13-μm silicide CMOS technology are also presented.     

Study on the Suppression of Gyro-BWO by Distributed Wall Losses

In this paper, the effect of distributed wall losses on the starting length and starting frequency of a TE₂₁ mode gyro-BWO is investigated for different operating magnetic fields by using a linear theory. Numerical results show that, for the efficient suppression of a gyro-BWO in a distributed wall losses gyro-TWA consisting of a lossy section followed by a copper section, the wall losses applied in the lossy section should be able to provide a cold attenuation approximately equal to the linear growth rate of the gyro-BWO in the case of wall losses neglected and the copper section length should be shorter than the starting length of the corresponding gyro-BWO without wall losses loaded.     

Eliminating small stopping sets in irregular low-density parity-check codes

We present a novel scheme to eliminate small stopping sets in irregular low-density parity-check (LDPC) codes. By adding several new check nodes and having their edges connected to small stopping sets in the original code, the improved code decreases the number of small stopping sets efficiently. Simulation results show that the proposed scheme decreases the frame error rate (FER) significantly in the error floor region, whereas having almost the same rate as the original code.     

无溶剂法生产β-环状糊精工艺的研究

目的:将超滤、纳滤技术应用于β-环状糊精生产中,得到无溶剂法生产β-环状糊精新工艺。方法以5%木薯淀粉和β-环状糊精葡萄糖基转移酶为原料,于85℃、pH 6.5进行淀粉的糊化和液化,在55℃、pH 7.0完成环化,生成β-环状糊精。选择不同截留分子量的膜组件,研究在不同膜组件分离过程中的分离条件,完成无溶剂法生产β-环状糊精。结果利用截留分子量为500Dalton的纳滤膜和截留分子量为10000Dalton的超滤膜联用,分离出酶促反应过程中生成的β-环状糊精,保证产品中没有溶剂溶剂的残留,真空干燥得成品,最终收率为33.63%。结论把膜分离技术应用于β-环状糊精生产,可以得到无溶剂法生产β-环状糊精的新工艺。     

响应面优化超声波辅助水酶法提取蜡梅籽蛋白

采用超声波辅助水酶法提取蜡梅籽蛋白,探讨超声波处理时间与温度、酶用量、碱浸提液pH、酶解温度、酶解时间及料液比对蜡梅籽蛋白提取效果的影响。应用Box-Behnken设计4因素3水平的试验,依据响应面分析确定最优的提取工艺条件。结果表明,最佳提取工艺参数为:超声波处理时间15min,超声波处理温度50℃,料液比1:8,酶用量3.64%,碱浸提pH9.72,酶解温度45℃,酶解时间163min。在此条件下,蜡梅籽蛋白的得率为31.95%。