Extreme Two‐Phase Cooling from Laser‐Etched Diamond and Conformal,Template‐Fabricated Microporous Copper

This paper reports the first integration of laser‐etched polycrystalline diamond microchannels with template‐fabricated microporous copper for extreme convective boiling in a composite heat sink for power electronics and energy conversion. Diamond offers the highest thermal conductivity near room temperature, and enables aggressive heat spreading along triangular channel walls with 1:1 aspect ratio. Conformally coated porous copper with thickness 25 µm and 5 µm pore size optimizes fluid and heat transport for convective boiling within the diamond channels. Data reported here include 1280 W cm^?2 of heat removal from 0.7 cm² surface area with temperature rise beyond fluid saturation less than 21 K, corresponding to 6.3 × 10⁵ W m^?2 K^?1. This heat sink has the potential to dissipate much larger localized heat loads with small temperature nonuniformity (5 kW cm^?2 over 200 µm × 200 µm with <3 K temperature difference). A microfluidic manifold assures uniform distribution of liquid over the heat sink surface with negligible pumping power requirements (e.g., <1.4 × 10^?4 of the thermal power dissipated). This breakthrough integration of functional materials and the resulting experimental data set a very high bar for microfluidic heat removal.     

直接调制应用中的混合分数N阶合成器

对减少元器件数量、提高性能的需求不断促使无线系统结构的革新，其中之一就是直接调制结构。直接调制适于采用调频方式的GSM、蓝牙和802.11b系统。系统发射部分的直接调制，直接将数据送入DS合成器的DS调制器部分。目前，对高速数据系统采用这项调制技术尚有困难，这是因为DS合成器环路带宽窄，不足以减少DS调制器在高频段产生的量化噪声。这种带宽较窄的锁相环滤波器一方面衰减量化噪音，另一方面，由于数据也被滤掉，会引起符号间干扰(ISI)。所以，为了在高速数据速率标准中使用直接调制结构，必须降低量化噪声。本文分析几种类型…     

Susceptible Workload Evaluation and Protection using Selective Fault Tolerance

Low power fault tolerance design techniques trade reliability to reduce the area cost and the power overhead of integrated circuits by protecting only a subset of their workload or their most vulnerable parts. However, in the presence of faults not all workloads are equally susceptible to errors. In this paper, we present a low power fault tolerance design technique that selects and protects the most susceptible workload. We propose to rank the workload susceptibility as the likelihood of any error to bypass the logic masking of the circuit and propagate to its outputs. The susceptible workload is protected by a partial Triple Modular Redundancy (TMR) scheme. We evaluate the proposed technique on timing-independent and timing-dependent errors induced by permanent and transient faults. In comparison with unranked selective fault tolerance approach, we demonstrate a) a similar error coverage with a 39.7% average reduction of the area overhead or b) a 86.9% average error coverage improvement for a similar area overhead. For the same area overhead case, we observe an error coverage improvement of 53.1% and 53.5% against permanent stuck-at and transition faults, respectively, and an average error coverage improvement of 151.8% and 89.0% against timing-dependent and timing-independent transient faults, respectively. Compared to TMR, the proposed technique achieves an area and power overhead reduction of 145.8% to 182.0%.     

A continuous-time delta-sigma modulator for 802.11a/b/g WLAN implemented with a hierarchical bottom-up optimization methodology

This paper presents a 3rd-order continuous-time Delta-Sigma modulator with a resolution of 10 bits for a 10 MHz signal bandwidth. It is designed in a standard 0.18 μm CMOS technology and consumes only 6 mW. After the design/selection of the topologies for the integrators, comparator and D/A converters, optimal sizing of the complete modulator was ensured by using a hierarchical bottom-up, multi-objective evolutionary design methodology. With this methodology, a set of Pareto-optimal modulator designs is generated by using Pareto-optimal performance solutions of the hierarchically decomposed lower-level subblocks. From the generated Pareto-optimal design set, a final optimal design is chosen that complies with the specifications for the 802.11a/b/g WLAN standard and has minimal power consumption.     

Conjugate-order systems for signal processing: stability, causality, boundedness, compactness

The fundamental system theory is presented for a class of real systems whose derivative order is complex. It is demonstrated that these so-called conjugate-order systems have a scale-invariance property in both the time and frequency domains, which makes them useful for describing certain phenomena in continuous media. The conditions for which these systems are guaranteed to be causal and stable are reviewed. The compactness properties of their Hankel operators, which allow them to admit finite-order approximations, are also discussed. A procedure is developed for choosing appropriate transfer-function parameter values to design a stable conjugate-order system whose frequency response meets given bandwidth, resonance, and ripple specifications.     

Quality Map Thresholding for De-noising of Complex-Valued fMRI Data and Its Application to ICA of fMRI

Although functional magnetic resonance imaging (fMRI) data are acquired as complex-valued images, traditionally most fMRI studies only use the magnitude of the data. FMRI analysis in the complex domain promises to provide more statistically significant information; however, the noisy nature of the phase poses a challenge for successful study of fMRI by complex-valued signal processing algorithms. In this paper, we introduce a physiologically motivated de-noising method that uses phase quality maps to successfully identify and eliminate noisy areas in the fMRI data so they can be used in individual and group studies. Additionally, we show how the developed de-noising method improves the results of complex-valued independent component analysis of fMRI data, a very successful tool for blind source separation of biomedical data.     

Evaluation of registration methods on thoracic CT: the EMPIRE10 challenge

EMPIRE10 (Evaluation of Methods for Pulmonary Image REgistration 2010) is a public platform for fair and meaningful comparison of registration algorithms which are applied to a database of intrapatient thoracic CT image pairs. Evaluation of nonrigid registration techniques is a nontrivial task. This is compounded by the fact that researchers typically test only on their own data, which varies widely. For this reason, reliable assessment and comparison of different registration algorithms has been virtually impossible in the past. In this work we present the results of the launch phase of EMPIRE10, which comprised the comprehensive evaluation and comparison of 20 individual algorithms from leading academic and industrial research groups. All algorithms are applied to the same set of 30 thoracic CT pairs. Algorithm settings and parameters are chosen by researchers expert in the configuration of their own method and the evaluation is independent, using the same criteria for all participants. All results are published on the EMPIRE10 website (http://empire10.isi.uu.nl). The challenge remains ongoing and open to new participants. Full results from 24 algorithms have been published at the time of writing. This paper details the organization of the challenge, the data and evaluation methods and the outcome of the initial launch with 20 algorithms. The gain in knowledge and future work are discussed.     

Low delay distributed video coding with refined side information

Distributed video coding (DVC) is a new video coding paradigm based upon two fundamental theoretical results: the Slepian–Wolf and Wyner–Ziv theorems. Among other benefits, this new coding paradigm may allow a flexible complexity allocation between the encoder and the decoder. Several DVC codecs have been developed over the years addressing the specific requirements of emerging applications such as wireless video surveillance and sensor networks. While state-of-the-art DVC codecs, such as the DISCOVER DVC codec, have shown promising RD performance, most DVC codecs in the literature do not consider low delay requirements which are relevant for some of the addressed applications. In this context, the main objective and novelty of this paper is to propose an efficient, low delay and fully practical DVC codec based on the Stanford DVC architecture adopting a side information iterative refinement approach. The obtained performance results show that the developed DVC solution fulfils the objectives regarding relevant benchmarks, notably due to the novel side information creation and correlation noise modeling tools integrated in a side information iterative refinement framework.     

System memory effects in the sizing of stand‐alone PV systems

Models based on daily energy balance (or long‐term models) have been widely used as a tool in the stand‐alone photovoltaic (PV) system sizing, mainly with the purpose of obtaining analytical expressions of the relation between the generator size and the storage capacity of the battery. The system can then be designed to meet the reliability requirements of the specific case. However, such models represent the complex operation of a stand‐alone system in an oversimplified way. There is little research so far on the reliability and improvement of such models. Validation and possible modification of a long‐term system model requires comparison of the simulated state of charge (SOC) of the battery with that obtained from an experimental system. In this work, experimental data from a 6‐month operation of a basic stand‐alone PV system have been analysed and compared with modelling results. One obvious improvement that could be applied to the long‐term system model is to account for a charging efficiency of the battery, and this possibility is examined in the present work. However, comparison with the modelling results shows that the data cannot be fitted by simply taking into account battery inefficiency. A method to account for system memory effects in the increase of the battery SOC, imposed by the operation of the regulator, is necessary to accurately model the macroscopic diurnal charging/discharging process. Copyright © 2012 John Wiley & Sons, Ltd.