A 146-mm/sup 2/ 8-gb multi-level NAND flash memory with 70-nm CMOS technology

An 8-Gb multi-level NAND Flash memory with 4-level programmed cells has been developed successfully. The cost-effective small chip has been fabricated in 70-nm CMOS technology. To decrease the chip size, a one-sided pad arrangement with compacted core architecture and a block address expansion scheme without block redundancy replacement have been introduced. With these methods, the chip size has been reduced to 146 mm/sup 2/, which is 4.9% smaller than the conventional chip. In terms of performance, the program throughput reaches 6 MB/s at 4-KB page operation, which is significantly faster than previously reported and very competitive with binary Flash memories. This high performance has been achieved by the combination of the multi-level cell (MLC) programming with write caches and with the program voltage compensation technique for neighboring select transistors. The read throughput reaches 60 MB/s using 16I/O configuration.     

High-input-power saturation properties of apolarization-insensitive semiconductor Mach-Zehnder interferometer gateswitch for WDM applications

We propose that a polarization-insensitive Mach-Zehnder interferometer (MZI) switch is useful for optical gate elements, especially if multiwavelength signals are input. This device has high-input-power saturation properties, which shows that both the operating voltage and the extinction ratio do not change when the optical input power reaches at least +18 dBm. A high extinction ratio of 30 dB was achieved in the wide-wavelength range of 20 nm. Moreover, the extinction ratio can be improved by up to 45 dB by using a cascaded configuration to decrease crosstalk. These results indicate the MZI gate switch is well suited to wavelength-division multiplexing (WDM) network components     

A real-time motion estimation and compensation LSI with wide searchrange for MPEG2 video encoding

This paper presents a motion estimation and compensation large scale integration (LSI) for the MPEG2 standard. An embedded RISC processor and special hardware modules enable the LSI to achieve a sufficient ability to perform real-time operation and provide the availability to realize many kinds of block matching algorithms. Using a three-step hierarchical telescopic search algorithm, a single chip accomplishes real-time motion estimation with search ranges of ±32.5×±32.5 pixels for motion vectors. The chip was fabricated using 0.5-μm CMOS technology and has an area of 16.5×16.5 mm² and 2.0 M transistors     

Decision-making in electrical appliance use in the home

This paper presents the results of a survey as well as an argument from the viewpoint of behavioral economics with the aim of clarifying how consumers make decisions about electrical appliance use in the home. A survey of consumers showed that most have little awareness of the energy efficiency of appliances, the price of the services produced by electrical appliances, or electricity rates. These findings indicate that price does not function as a signal in electricity consumption through electrical appliance use. Rather, we found that consumer decision-making in electricity consumption is dependent on the characteristics of the particular electrical appliances they use. Additionally, we argue that the payment system for home electricity consumption plays an important role in decision-making, causing biases due to aspects of human psychology discussed here in terms of satisficing and heuristics, payment decoupling, and budgeting. We conclude that decision-making about electrical appliance use and electricity consumption in the home is not always rational and is affected both by the particular characteristics of appliances and the payment system for electricity consumption along with human psychology.     

Influence of buried structure on polarization sensitivity instrained bulk semiconductor optical amplifiers

In order to achieve an accurate design of polarization-insensitive semiconductor optical amplifiers based on tensile strained bulk InGaAsP, the reduction of strain in the active layer of the buried heterostructure and its influence on polarization sensitivity are analyzed numerically for the first time. The gain calculation, including the strain distribution in the active layer, is examined based on the k · p method for the different active layers. It is found that the strain introduced during the epitaxial growth is strongly reduced after regrowth of the burying layer. In an active layer having the aspect ratio of 1 : 4, the strain reduction causes more than a 0.5-dB deviation in the polarization sensitivity of the gain. From a comparison with the experimental results, it is shown that including the effect of the burying layer in the calculation gives an accurate determination of the amount of strain for the polarization independence     

1-GHz-spaced 16-channel arrayed-waveguide grating for a wavelength reference standard in DWDM network systems

We fabricated a 1-GHz-spaced 16-channel arrayed-waveguide grating (AWG) by using a new AWG configuration where the path of each arrayed waveguide winds backward and forward across a 4-in diameter wafer without crossing any other waveguides. The ultra-narrow (< 1 GHz) and stable transmission bands of this AWG can be used to construct a wavelength reference standard covering the S, C, and L bands in the dense wavelength-division-multiplexing network systems whose frequency deviation is /spl plusmn/160 MHz.     

1.5%-/spl Delta/ athermal arrayed-waveguide grating multi/demultiplexer with very low loss groove design

We describe a compact 1.5%-/spl Delta/ athermal silica-based 100-GHz-spacing 16-channel arrayed-waveguide grating (AWG) multi/demultiplexer with a modified groove design for a very low excess loss. We propose new approaches for modifying the shape of the grooves and the arrayed waveguides and optimize the shape modifications for 1.5%-/spl Delta/ waveguides. By employing this modified groove design, we greatly reduced the groove excess loss from 1.9 to 0.4 dB in the 1.5%-/spl Delta/ athermal AWG.     

Low-loss athermal silica-based lattice-form interleave filter with silicone-filled grooves

We describe a low-loss athermal silica-based interleave filter with a lattice-form structure. We athermalize the filter by using a silicone-filled groove formed in each delay line and we employ a low-loss design to reduce the accumulated groove excess loss in the multiple delay lines. By using these designs, we obtained a very low groove excess loss of 0.4 dB and achieved satisfactory temperature insensitivity and optical characteristics with this filter.     

Extremely low-loss 1.5%-/spl Delta/ 32-channel athermal arrayed-waveguide grating multi/demultiplexer

A silica-based 1.5%-/spl Delta/ 100 GHz-spacing 32-channel athermal arrayed-waveguide grating (AWG) with compact size and extremely low insertion loss is described. By reducing the fibre coupling loss and the excess loss in a silicone-filled groove, an insertion loss of 1.3 dB was achieved with this athermal AWG.     

A delay-encoding-logic array processor for dynamic-programming matching of data sequences

Computationally very expensive dynamic-programming matching of data sequences has been directly implemented in a fully-parallel-architecture VLSI chip. The circuit operates as digital logic in the signal domain, while analog processing is carried out in the time domain based on the delay-encoding-logic scheme. As a result, a high-speed low-power best-match-sequence search has been established with a small chip area. The typical matching time of 80 ns with the power dissipation of 2 mW has been demonstrated with fabricated prototype chips.